Multiplexer configuration for programmable logic device
AssigneeAltera Corporation
InventorsPaul Metzgen, Dominic Nancekievill
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Abstract
A multiplexer is configured on a programmable logic device using a plurality of four-input look-up tables chained together. The required number of look-up tables is about one-half the number of inputs of the multiplexer. For an even number of inputs, the number of look-up tables preferably is exactly one-half the number of inputs, while for an odd number of inputs, the number of look-up tables preferably is one-half the number of inputs, plus one-half. The number of control inputs preferably is one more than the number of look-up tables. Preferably, for any one input being a given logic state, and further selected by the one extra input (beyond the number of look-up tables), any particular output may be asserted.
Claims47
A multiplexer circuit in a programmable logic device, said multiplier circuit having a circuit output and comprising:
- N data inputs, where N≧6;
- C control inputs;
- and
- L look-up tables, each having only one table output, wherein:
- L=0.5(N+MOD(N,2));
- C=L+1;
- each of L−2 of said L look-up tables has, as an input, a table output of another one of said L look-up tables, and has its table output directed only to an input of another one of said L look-up tables;
- one of said L look-up tables other than said L−2 look-up tables has its table output directed only to an input of one of said L−2 look-up tables;
- and
- another one of said L look-up tables, other than said L−2 look-up tables and said one of said L look-up tables, has as an input the table output of one of said L−2 look-up tables, the output of said another one of said L look-up tables being said circuit output.
A multiplexer circuit having a circuit output, N data inputs and C control inputs, and comprising L four-input loot-up tables, each having only one table output, wherein N≧6, L=0.5(N+MOD(N,2)) and C=L+1;
- said L look-up tables comprising:
- a first look-up table having, as inputs, two of said N data inputs and two of said C control inputs, said only one table output of said first look-up table being connected as input to a second look-up table;
- an Lth look-up table having, as inputs, two of said N data inputs, one of said C control inputs and said only one table output of an (L−1)th look-up table, said only one table output of said Lth look-up table being said circuit output;
- and
- second through (L−1)th look-up tables, each having, as inputs, two of said N data inputs, one of said C control inputs and a table output of another of said L look-up tables, said only one table output of each of said second through (L−1)th look-up tables being an input to another of said L look-up tables.
A multiplexer circuit comprising:
- L look-up tables;
- a plurality of data inputs, each of said data inputs being connected to one of said L look-up tables;
- and
- C control inputs;
- wherein:
- C=L+1;
- each of said L look-up tables has as an input only one of said C control inputs, except for a first look-up table, which also has as an input an extra one of said C control inputs;
- and
- at any one time, only one of said C control inputs is in a first logic state, with each other of said C control inputs in a second logic state different from said first logic state, except for said extra one of said C control inputs which may be in either said first logic state or said second logic state.
A method for encoding control inputs of a multiplexer, said multiplexer comprising L interconnected look-up tables and having C said control inputs, said method comprising:
- providing a respective one of said C control inputs to each of said L look-up tables;
- providing another one of said C control inputs to only one of said L look-up tables, whereby C=L+1;
- and
- at any one time, asserting only one of said C control inputs in a first logic state, with each other of said C control inputs in a second logic state different from said first logic state, except for said second one of said C control inputs which may be in either said first logic state or said second logic state.
Dependencies are inferred from the claim text.