US 7,002,369 B2 · Implementing complex clock designs in field programmable devices

Abstract

An aspect of the present invention simplifies the implementation of complex clock designs in field programmable devices (FPD). To implement a circuit logic containing base sequential elements (e.g., D flip-flops) with corresponding circuit clocks, a number of modified sequential elements equaling the number of base sequential elements may be employed. Each modified sequential element (contained in FPD) receives a global clock, corresponding circuit clock and a data value. A base sequential element (contained in modified sequential element) transitions to a next state only after occurrence of a transition on a corresponding circuit clock and the transition to said next state may be timed according to the global clock. By timing the transitions according to the global clock, several undesired results may be avoided.

Claims9

Dependent claims

A field programmable device (FPD) implementing a circuit logic containing a first base sequential element to be clocked by a first circuit clock and a second base sequential element to be clocked by a second circuit clock, said FPD comprises:

a first modified sequential element to receive a global clock and said first circuit clock, said first modified sequential element containing said first base sequential element, said global clock being connected to a clock input of said first base sequential element, said first base sequential element transitioning to a next state only after occurrence of a transition on said first circuit clock and transition to said next state being timed according to said global clock;
and
a second modified sequential element to receive said global clock and said second circuit clock, said second modified sequential element containing said second base sequential element, said global clock being connected to a clock input of said second base sequential element, said second base sequential element transitioning to a next state only after occurrence of a transition on said second circuit clock and transition to said next state being timed according to said global clock.

Dependencies are inferred from the claim text.

Implementing complex clock designs in field programmable devices

Life of this patent

Implementing complex clock designs in field programmable devices

Life of this patent

Abstract

Claims9