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US 7,002,365 B2Granted
Method and an apparatus for testing transmitter and receiver
AssigneeIntel Corporation
InventorsAkira Kakizawa, Ronald W. Swartz
Life of this patent
Estimating the term…
Abstract
A method and an apparatus for testing transmitter and receiver have been disclosed. One embodiment of the apparatus includes a plurality of multiplexers to select one of a positive transmitter pin and a negative transmitter pin, and a first comparator to compare a voltage of the selected pin with a first reference voltage to determine whether leakage exists at the selected pin. Other embodiments are described and claimed.
Claims11
A semiconductor device comprising:
- a plurality of multiplexers to select one of a positive and a negative transmitter pins as a selected transmitter pin;
- a first comparator to compare a voltage of the selected pin with a first reference voltage to determine whether there is leakage at the selected pin;
- a first plurality of termination resistors coupled to the positive transmitter pin;
- and
- a second plurality of termination resistors coupled to the negative transmitter pin such that each of the first and second pluralities of termination resistors are tested with the first reference voltage and the first comparator.
2 more elements
A method to test an input/output of a semiconductor device, the method comprising:
- selecting one of a positive transmitter pin and a negative transmitter pin as a selected transmitter pin;
- comparing a voltage at the selected transmitter pin with a first reference voltage using a first comparator in the semiconductor device to determine whether there is leakage at the selected transmitter pin;
- selecting one or more of a plurality of termination resistors as selected termination resistors;
- and
- testing the selected termination resistors with the first reference voltage and the first comparator.
2 more elements
A computer system comprising:
- a plurality of dynamic random access memory devices (DRAM);
- and
- a chipset coupled to the plurality of DRAMs, the chipset including a semiconductor device that comprises
- a plurality of multiplexers to select one of a positive and a negative transmitter pins as a selected transmitter pin;
- a first comparator to compare a voltage of the selected pin with a first reference voltage to determine whether there is leakage at the selected pin;
- a first plurality of termination resistors coupled to the positive transmitter pin;
- and
- a second plurality of termination resistors coupled to the negative transmitter pin such that each of the first and second pluralities of termination resistors are tested using the first reference voltage and the first comparator.
5 more elements
Dependencies are inferred from the claim text.