Wiring structure of a semiconductor integrated circuit and a method of forming the wiring structure
AssigneeKawasaki Microelectronics, Inc.
InventorHiroshi Yamamoto
Life of this patent
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Abstract
A wiring structure for effectively reducing wiring capacitance, and a method of forming the wiring structure is disclosed. An underlying film having a dielectric constant lower than that of silicon oxide is formed on at least side surfaces of the wires of a wiring layer and a low dielectric constant film having an even lower dielectric constant is formed between the wires. Further, the surfaces of the underlying film are positively sloped. Because the low dielectric constants of the underlying film and the low dielectric constant film, wiring capacitance is effectively reduced. Further, the positively sloped surfaces facilitate the filling of narrow spaces between the wires by the low dielectric constant film.
Claims43
A semiconductor integrated circuit, comprising:
- a semiconductor substrate;
- at least two copper-based wiring layers disposed over the semiconductor substrate, wherein a plurality of fat wires are formed in the at least two copper-based wiring layers;
- and
- a top-most aluminum-based wiring layer disposed over the copper-based wiring layers, wherein the copper-based wiring layers are formed of a different material from, and have a lower resistance than, the aluminum-based wiring layer.
A semiconductor integrated circuit, comprising:
- a semiconductor substrate;
- at least two copper-based wiring layers disposed over the semiconductor substrate, wherein a plurality of low resistance wires are formed in the at least two copper-based wiring layers;
- and
- a top-most aluminum-based wiring layer disposed over the copper-based wiring layers, wherein the copper-based wiring layers are formed of a different material from, and have a lower resistance than, the aluminum-based wiring layer,
- and wherein the plurality of low resistance wires are used in a long distance signal wiring to connect a circuit block to an I/O cell or to a second circuit block.
The semiconductor integrated circuit according to clam 12, wherein the dielectric constant of the low dielectric constant film is about 3.0 or less.
A method of forming a semiconductor integrated circuit, comprising the steps of:
- forming fat wires in at least two copper-based wiring layers over a semiconductor substrate;
- and
- adding an aluminum-based wiring layer over the at least two copper-based wiring layers as a top-most wiring layer, wherein the at least two copper-based wiring layers are formed of a different material from, and having a lower resistance than, the aluminum-based wiring layer.
A semiconductor integrated circuit, comprising:
- a semiconductor substrate;
- at least a first copper-based wiring layer disposed over the semiconductor substrate, wherein a plurality of first fat wires are formed in the first copper-based wiring layer;
- at least a second copper-based wiring layer disposed over the semiconductor substrate, wherein a plurality of second fat wires are formed in the second copper-based wiring layer;
- and
- a top-most aluminum-based wiring layer disposed over the first and the second copper-based wiring layer, wherein the first and the second copper-based wiring layer are formed of a different material from, and having a lower resistance than, the aluminum-based wiring layer,
- and wherein the first fat wires are used in a long distance signal wiring to connect a circuit block to an I/O cell or to a second circuit block, and the second fat wires are used in a power bus wiring.
Dependencies are inferred from the claim text.