Microelectronic component with reduced parasitic inductance and method of fabricating

#U.S. patent application Ser. No. 10/237,903, filed on Sep. 9, 2002, by Thomas P. Duffy, Malay Trivedi, and Kevin Mori, entitled: SYSTEM AND METHOD FOR CURRENT HANDLING IN A DIGITALLY-CONTROLLED POWER CONVERTER, now U.S. Pat. No. 6,795,009.

#1. Technical Field

#The present invention relates, generally, to the packaging of semiconductor chips and, more particularly, to wire bond techniques effective in reducing parasitic inductance in microelectronic components, i.e. packaged semiconductor chips.

#The subject invention will hereinafter be described in conjunction with the appended drawing figures, which are provided for purposes of illustration and not limitation, wherein like numerals denote like elements, and:

#FIG. 1 is a schematic diagram of a typical DC voltage regulator integrated circuit;

#FIG. 2 is a top view schematic of a typical Quad Flat Non-leaded (QFN) lead frame package;

#Systems and methods in accordance with the present invention overcome the prior art by providing a semiconductor device package with inter-digitated input and output bond wires configured to increase the negative mutual inductive coupling between the wires, thus reducing the overall parasitic inductance of the device.

#Referring now to FIG. 3A, a microelectronic component in accordance with the present invention generally includes a semiconductor chip 150 bonded to a lead frame (not shown), a first set of bond wires 152 connected to semiconductor chip 150 (e.g., via bond pads 156) for providing current flow into the semiconductor device, and a second set of bond wires 154 that are in a current loop with the first set of bond wires 152 and are connected to semiconductor device 150 for providing current flow out of the semiconductor device. As shown, bond wires 152 are inter-digitated with bond wires 154 in order to increase the magnitude of mutual inductive coupling between the two sets of wires. Alternatively, multiple wires from each of the first and second sets of bond wires may be inter-digitated as shown in FIG. 3B, where, for example, pairs of input wires 152 are inter-digitated with pairs of output wires 154. Although the bond wires 152 and 154 are shown on only one side of the chip 150, in FIGS. 3A and 3B such inter-digitating can also be done on two or more sides of the chip.

#A still further alternative is illustrated in FIG. 3C. Input wires 152 and output wires 154 are shown as in FIG. 3B. However, in this alternative contact pads are located not only on the periphery of the semiconductor chip 150, but also in the interior of the chip surface. Thus, on the left side of the chip, contacts 156 are at the periphery of the chip while contacts 157 are at the interior of the chip surface. In this configuration, the chip is accessed from both the left and right sides of the chip by way of peripheral pads and interior pads. On the right side of the chip, peripheral pads 158 and interior pads 159 are provided. Input wires 160 and output wires 162 are connected on the right side of the chip, as shown.