Integrated semiconductor memory circuit and method of manufacturing the same
AssigneeInfineon Technologies AG
InventorMichael Bernhard Sommer
Life of this patent
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Abstract
An integrated semiconductor circuit, having active components lying in mutually adjoining wells of a respective first and second conduction type, wherein the active components respectively are associated with substrate contacts lying in direct proximity to an edge bounding the mutually adjoining wells, is disclosed. Preferably, structures of the active components other than the contacts are arranged to lie further away from the edge and the circuit/layout structures are not mirror-symmetrical with respect to a center line of the circuit chip.
Claims16
A semiconductor device comprising:
- a plurality of wells of a first conduction type, each well formed in a substrate and containing a first set of active components and a first set of contacts associated with the first set of active components;
- and
- a plurality of wells of a second conduction type, each well formed in a substrate and containing a second set of active components and a second set of contacts associated with the active components,
- wherein the wells of the first conduction type share a mutually adjoining boundary with the wells of the second conduction type, the mutually adjoining boundary disposed within a border region, wherein a contamination zone due to implantation scattering during well implantation lies within the border region;
- wherein the first set of contacts and second set of contacts lie in the border region near the mutually adjoining boundary, and
- wherein the active components lie further away from the mutually adjoining boundary than do the first and second set of contacts.
A semiconductor chip comprising:
- a plurality of pairs of wells, each pair including an n-type well adjacent to a p-type well, wherein a border region is defined along an edge where each n-well and p-well are mutually adjacent;
- a set of contacts within each well arranged to lie within the border region;
- and
- a set of active components within each well arranged to lie outside the border region;
- wherein the arrangement of the pairs of wells is such that there is no mirror symmetry of the well location with respect to a line through the center of the chip;
- and
- wherein a contamination zone due to implantation scattering during well implantation lies within the border region within each pair of wells.
A semiconductor device comprising:
- a plurality of pairs of wells, each pair including an n-type well adjacent to a p-type well, wherein a border region is defined along an edge where each n-well and p-well are mutually adjacent, wherein a contamination zone due to implantation scattering during well implantation lies within the border region within each pair of wells;
- at least one contacts within each well arranged to lie within the border region;
- and
- at least one active component within each well arranged to lie outside the border region.
Dependencies are inferred from the claim text.