ESD protection circuit
AssigneeMarvell International Ltd.
InventorsXiaodong Jin, Sehat Sutardja, Lawrence Tse, King Chun Tsai
Life of this patent
Estimating the term…
Abstract
An electrostatic discharge (ESD) protection circuit is provided for protecting transistors of an integrated circuit (IC) from ESD. The ESD protection circuit includes n transistors with n gates and less than n drains where n is an integer greater than 1. At least m resistors have first ends that communicate with at least one of the transistors of the IC, a blocking capacitor of the IC, an input pad of the IC, and an output pad of the IC, and second ends that connect to corresponding drain terminals of said drains where m is an integer greater than or equal to n/2.
Claims42
An electrostatic discharge (ESD) protection circuit for protecting transistors of an integrated circuit (IC) from ESD, comprising:
- n transistors with n gates and less than n drains where n is an integer greater than 1;
- and
- at least m resistors that have first ends that communicate with at least one of the transistors of the IC, a blocking capacitor of the IC, an input pad of the IC, and an output pad of the IC, and second ends that are connected to corresponding drain terminals of said drains where m is an integer greater than or equal to n/2.
A method for reducing a parasitic capacitance of an electrostatic discharge (ESD) protection circuit for an integrated circuit (IC), comprising:
- providing an ESD protection circuit including n transistors and less than n drains where n is an integer greater than 1;
- coupling ends of at least m resistors to drain terminals of said drains of said transistors;
- and
- coupling opposite ends of said at least m resistors to at least one of an input pad of the IC, an output pad of the IC, a blocking capacitor of the IC and a transistor in the IC where m is an integer greater than or equal to n/2.
An electrostatic discharge (ESD) protection circuit for protecting transistors of an integrated circuit (IC) from ESD, comprising:
- n transistors with n gates and less than n drains where n is an integer greater than 1;
- at least m resistors that have first ends that communicate with at least one of the transistors of the IC, a blocking capacitor of the IC, an input pad of the IC, and an output pad of the IC;
- and
- a first connection that is formed one of during fabrication and after fabrication that connects a second end of at least one of said at least m resistors to a corresponding drain terminal of said drains where m is an integer greater than or equal to n/2.
A method for adjusting a capacitance of an electrostatic discharge (ESD) protection circuit that protects transistors of an integrated circuit (IC) from ESD, comprising:
- providing n transistors with n gates and less than n drains where n is an integer greater than 1;
- providing at least m resistors where m is an integer greater than or equal to n/2;
- connecting first ends of said at least m resistors with at least one of the transistors of the IC, a blocking capacitor of the IC, an input pad of the IC, and an output pad of the IC;
- and
- forming a first connection one of during fabrication and after fabrication of said ESD circuit between a second end of at least one of said at least m resistors and a corresponding drain terminal of said drains.
An electrostatic discharge (ESD) protection circuit for protecting transistors of an integrated circuit (IC) from ESD, comprising:
- n transistors with n gates and less than n drains where n is an integer greater than 1;
- at least m resistors that have first ends that communicate with at least one of the transistors of the IC, a blocking capacitor of the IC, an input pad of the IC, and an output pad of the IC where m is an integer greater than or equal to n/2;
- and
- first connecting means that is formed one of during fabrication and after fabrication for connecting a second end of at least one of said at least m resistors to a corresponding drain terminal of said drains.
Dependencies are inferred from the claim text.