Ultra-thin body super-steep retrograde well (SSRW) FET devices

A method of manufacture of a Super Steep Retrograde Well (SSRW) FET (Field Effect Transistor) device comprising:

• forming an SOI layer on a substrate;
• thinning said SOI layer to form an ultra-thin SOI layer;
• forming an isolation trench separating said SOI layer into N and P wells and ground plane regions;
• doping the N and P wells and ground plane regions formed from said SOI layer with N-type and P-type dopant respectively;
• forming intrinsic semiconductor channel regions above said N and P wells and around plane regions;
• forming gate electrode stacks above said channel regions and forming FET source and drain regions;
• and
• forming a diffusion retarding barrier in the surface of said N and P wells and ground plane regions.

A Super Steep Retrograde Well (SSRW) FET (Field Effect Transistor) device comprising:

• an ultra-thin SOI layer formed on a substrate;
• an isolation trench separating said SOI layer into a N type doped N well and a P type doped P well including ground plane regions in said N well and in said P well, each of said N well and said P well having a top surface;
• an epitaxial semiconductor layer formed on said top surfaces of said N well and said P well;
• gate electrode stacks formed above said epitaxial semiconductor layer with channel regions therebelow;
• and
• FET source regions and drain regions formed in said epitaxial layer and in both said N well and said P well.