Transistor and logic circuit on thin silicon-on-insulator wafers based on gate induced drain leakage currents

A NOR logic circuit having a first input and a second input comprising:

• a semiconductor substrate;
• an insulator formed on said semiconductor substrate;
• a semiconductor layer formed on said insulator;
• a n− well formed in said semiconductor layer, said n-well being the output of said NOR gate;
• a first gate structure formed atop said n-well, said first gate structure being the first input and being formed from a thin gate oxide layer underneath a conductive layer;
• a second gate structure formed atop said n-well, said second gate structure being the second input and being formed from a thin gate oxide layer underneath a conductive layer;
• a p+ structure formed adjacent to a first edge of said first gate structure and said second gate structure;
• a second p+ structure adjacent to a second edge of said first gate structure and said second gate structure, said second p+ structure being the output of said NOR logic circuit;
• a first switch formed in said semiconductor layer, said first switch electrically connected to said first input;
• and
• a second switch formed in said semiconductor layer in series to said first switch and electrically connected to said second input, said second switch also electrically connected to said second p+ structure.