MOSFET structure with high mechanical stress in the channel

#The present invention relates to semiconductor devices having enhanced electron and hole mobilities, and more particularly, to semiconductor devices that include a silicon (Si)-containing layer having enhanced electron and hole mobilities. The present invention also provides methods for forming such semiconductor devices.

#For more than three decades, the continued miniaturization of silicon metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. A concise summary of near-term and long-term challenges to continued complementary metal oxide semiconductor (CMOS) scaling can be found in the “Grand Challenges” section of the 2002 Update of the International Technology Roadmap for Semiconductors (ITRS). A very thorough review of the device, material, circuit, and systems can be found in Proc. IEEE, Vol. 89, No. 3, March 2001, a special issue dedicated to the limits of semiconductor technology.

#Since it has become increasingly difficult to improve MOSFETs and therefore CMOS performance through continued scaling, methods for improving performance without scaling have become critical. One approach for doing this is to increase carrier (electron and/or hole) mobilities. Increased carrier mobility can be obtained, for example, by introducing the appropriate stress into the Si lattice.

#FIG. 1 is a pictorial representation (through a cross-sectional view) showing a prior FET incorporating a nitride liner deposited atop a gate region and atop the top surface of a planar substrate; note the nitride liner is not located directly atop an exposed surface of the substrate adjacent the gate region due to the presence of the permanent spacers.

#FIG. 2 is a pictorial representation (through a cross-sectional view) of one embodiment of the inventive semiconducting device including a stress inducing liner located in close proximity to the gate region.

#FIG. 3 is a plot of the internal stress within the device channel produced by the stress inducing liner versus the thickness of the sidewall spacer adjacent to the gate region, where the internal stress is measured at the interface of the stress induced liner, the gate dielectric, and the substrate.

#The present invention provides a field effect transistor (FET), and a method of forming thereof, comprising a gate structure on a semiconducting substrate, in which a longitudinal stress is applied to a portion of the semiconducting substrate underlying the gate region to increase the FET's performance. The present invention advantageously provides a longitudinal stress to the portion of the substrate underlying the gate region by forming a stress inducing liner positioned in close proximity to the gate region and atop a surface of the substrate adjacent to and planar with the portion of the substrate on which the gate region is formed. The present invention is now discussed in more detail referring to the drawings that accompany the present application. In the accompanying drawings, like and/or corresponding elements are referred to by like reference numbers. In the drawings, a single gate region is shown and described. Despite this illustration, the present invention is not limited to a structure including a single gate region. Instead, a plurality of such gate regions is contemplated.

#Referring to FIG. 2, in one embodiment of the present invention, a field effect transistor (FET) 20 is provided, in which a longitudinal stress is produced in the device channel 12 of the substrate 10. The longitudinal stress in the device channel 12 of the FET 20 is provided by a stress inducing liner 15′ positioned atop the gate region 5 and atop the exposed surface 9 of the substrate 10 adjacent to the gate region 5. The substrate 10 also comprises source/drain regions 6 and extension regions 7. The device channel 12 is positioned between the extension regions 7 and beneath the gate region 5. A silicide contact 11 is located on a portion of the surface of the substrate 10 overlying the source/drain regions 6. The silicide contact 11 is spaced apart from the gate region 5 by an exposed surface of the substrate 10, in which the extension regions 7 are located.

#The gate region 5 comprises a gate conductor 3 atop a gate dielectric 2. The gate region 5 further comprises a gate cap 8, which is optional. The portion of the substrate 10 on which the gate region 5 is formed is hereafter referred to as the gate surface 21. Preferably, a thin sidewall spacer 4 abuts the gate region 5. The thin sidewall spacer 4 typically comprises an oxide, such as SiO2, and has a thickness ranging from about 1 nm to about 20 nm. The thin sidewall spacer 4 may be omitted.