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AssigneeKabushiki Kaisha Toshiba
InventorYoshiaki Fukuzumi
Estimating the term…
A semiconductor device includes a MOS transistor, interlayer dielectric film, first and second high-dielectric-constant films, and first and second conductive films. The MOS transistor is formed on a semiconductor substrate. The interlayer dielectric film is formed on the semiconductor substrate so as to cover the MOS transistor. The first high-dielectric-constant film is formed on the interlayer dielectric film and has an opening portion that reaches the interlayer dielectric film. The first conductive film contains a metal element and is formed to be partially embedded in the opening portion. The second high-dielectric-constant film is formed on the first conductive film. The second conductive film is formed on the second high-dielectric-constant film.
A semiconductor device comprising:
A semiconductor device comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
The capacitor extending over the transistor: making a connection between the transistor and the capacitor, e.g. plug
Of capacitors having no potential barriers: using deposition processes to form electrode extensions
Having non-planar surfaces, e.g. formed by texturisation: having vertical extensions
Having a storage electrode stacked over the transistor: with the capacitor higher than a bit line
Term ended 11 Dec 2022 (estimated)
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-383469, filed Dec. 17, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device and method of manufacturing the same and, more particularly, to a technique for improving the reliability of a DRAM (Dynamic Random Access Memory).
FIG. 1A is a plan view of a DRAM according to the first embodiment of the present invention;
FIG. 1B is a sectional view taken along a line 1B—1B in FIG. 1A;
FIGS. 2A to 2G are sectional views sequentially showing the steps in manufacturing the DRAM according to the first embodiment of the present invention;
A semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. 1A and 1B. FIG. 1A is a plan view of a DRAM which employs a double-surface-cylinder stacked capacitor structure for a cell capacitor. FIG. 1B is a sectional view taken along a line 1B—1B in FIG. 1A.
As shown in FIGS. 1A and 1B, a plurality of element regions AA where memory cells should be formed stagger in a silicon substrate 10. Referring to FIG. 1A, hatched regions indicate the element regions AA. Regions except the element regions AA are element isolation regions STI.
Gate electrodes 11 are formed on the silicon substrate 10 with gate insulating films 12 interposed therebetween. Each gate electrode 11 has a two-layered structure including, e.g., a polysilicon film 11a and tungsten film (W) 11b. The gate electrodes 11 are formed into a stripe that extends across the plurality of element regions AA in a direction perpendicular to the longitudinal direction of the element regions AA. Each gate electrode 11 functions as a word line WL and is connected to a row decoder (not shown). Impurity diffusion layers (not shown) serving as source and drain regions are selectively formed in the silicon substrate 10, thereby forming cell transistors.