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US 7,002,198 B2Granted
Junction-isolated depletion mode ferroelectric memory devices
AssigneeMicron Technology, Inc.
InventorsCraig T. Salling, Brian W. Huber
Life of this patent
Estimating the term…
Abstract
Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.
Claims21
A memory cell, comprising:
- a conductively-doped polysilicon layer having a first conductivity type formed overlying a substrate having the first conductivity type;
- a ferroelectric transistor formed overlying the polysilicon layer, wherein the transistor has a control gate, a ferroelectric layer interposed between the polysilicon layer and the control gate, a first source/drain region having the first conductivity type formed in the polysilicon layer, a second source/drain region having the first conductivity type formed in the polysilicon layer, and a channel having the first conductivity type formed in the polysilicon layer interposed between the first and second source/drain regions;
- and
- a well region having a second conductivity type opposite the first conductivity type, wherein the well region is interposed between the second source/drain region and the substrate.
1 more element
A memory cell, comprising:
- a conductively-doped polysilicon layer having a first conductivity type formed overlying a substrate having the first conductivity type;
- a ferroelectric transistor formed overlying the polysilicon layer, wherein the transistor has a control gate coupled to a word line, a ferroelectric layer interposed between the polysilicon layer and the control gate, a first source/drain region having the first conductivity type formed in the polysilicon layer and coupled to a program line, a second source/drain region having the first conductivity type formed in the polysilicon layer, and a channel having the first conductivity type formed in the polysilicon layer interposed between the first and second source/drain regions;
- and
- a well region having a second conductivity type opposite the first conductivity type, wherein the well region is formed in the substrate and wherein the well region is interposed between the second source/drain region and a bit line.
1 more element
A memory cell, comprising:
- a conductively-doped polysilicon layer having a first conductivity type formed overlying a substrate having the first conductivity type;
- a ferroelectric transistor formed overlying the polysilicon layer, wherein the transistor has a control gate, a ferroelectric layer interposed between the polysilicon layer and the control gate, a conductive floating gate interposed between the ferroelectric layer and the polysilicon layer, a gate dielectric layer interposed between the conductive floating gate and the polysilicon layer, a first source/drain region having the first conductivity type formed in the polysilicon layer, a second source/drain region having the first conductivity type formed in the polysilicon layer, and a channel having the first conductivity type formed in the polysilicon layer interposed between the first and second source/drain regions;
- and
- a well region having a second conductivity type opposite the first conductivity type, wherein the well region is interposed between the second source/drain region and the substrate and coupled to the second source/drain region by a conductive plug.
1 more element
A memory cell, comprising:
- a conductively-doped polysilicon layer having a first conductivity type formed overlying a substrate having the first conductivity type;
- a ferroelectric transistor formed overlying the polysilicon layer, wherein the transistor has a control gate, a ferroelectric layer interposed between the polysilicon layer and the control gate, a gate dielectric layer interposed between the ferroelectric layer and the polysilicon layer, a first source/drain region having the first conductivity type formed in the polysilicon layer, a second source/drain region having the first conductivity type formed in the polysilicon layer, and a channel having the first conductivity type formed in the polysilicon layer interposed between the first and second source/drain regions;
- and
- a well region having a second conductivity type opposite the first conductivity type, wherein the well region is interposed between the second source/drain region and the substrate and coupled to the second source/drain region by a conductive plug.
1 more element
A memory cell, comprising:
- a conductively-doped polysilicon layer having a first conductivity type formed overlying a substrate having the first conductivity type;
- a ferroelectric transistor formed overlying the polysilicon layer, wherein the transistor has a control gate, a ferroelectric layer interposed between the polysilicon layer and the control gate, a first source/drain region having the first conductivity type formed in the polysilicon layer, a second source/drain region having the first conductivity type formed in the polysilicon layer, and a channel having the first conductivity type formed in the polysilicon layer interposed between the first and second source/drain regions;
- and
- a well region having a second conductivity type opposite the first conductivity type, wherein the well region is interposed between the second source/drain region and the substrate and coupled to the second source/drain region by a conductive plug;
- wherein the ferroelectric layer is adjoining the polysilicon layer.
2 more elements
Dependencies are inferred from the claim text.