Polycrystalline silicon thin film transistor and method for fabricating the same

#The present invention claims the benefit of Korean patent application No.2002-0020467 filed in Korea on Apr. 15, 2002, which is hereby incorporated by reference.

#1. Field of the Invention

#The present invention relates to a thin film transistor (TFT) and a method for fabricating the same, and more particularly, to a polycrystalline silicon thin film transistor (poly-Si TFT) and a method of fabricating the same that decreases leakage current and improves electrical characteristics of the TFT.

#The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and together with the description serve to explain the principle of the invention. In the drawings:

#FIGS. 1A to 1E are cross-sectional views of a polycrystalline silicon thin film transistor according to the related art;

#FIGS. 2A to 2D are cross-sectional views of another polycrystalline silicon thin film transistor having dual gate electrodes according to the related art;

#Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.

#FIGS. 3A to 3D are cross-sectional views of an exemplary polycrystalline silicon thin film transistor according to the present invention. In FIG. 3A, a buffer layer 102 may be formed on a substrate 100. The buffer layer 102 may be a silicon insulating material, such as silicon nitride (SiNx) or silicon oxide (SiO2). Also, a polycrystalline silicon layer may be formed on the buffer layer 102, and may be subsequently patterned to form an island-shaped polycrystalline silicon active layer 104. For example, the polycrystalline silicon active layer 104 may be formed by applying a dehydrogenation method on an amorphous silicon layer and then converting the amorphous silicon layer into a polycrystalline silicon layer by a laser crystallization method. Further, a buffer layer 102 may function to prevent diffusion of alkali materials from the substrate 100 into the polycrystalline silicon active layer 104 when heat is applied to the substrate 100.

#In FIG. 3B, a gate insulation layer 106 may be formed over an entire surface of the buffer layer 102 to cover the active layer 104. The gate insulation layer 106 may be an inorganic material, such as silicon nitride (SiNx) or silicon oxide (SiO2). In addition, a dual-gate electrode having first and second gate electrodes 108a and 108b may be formed on the gate insulation layer 106 above portions of the active layer 104. A distance between the first and second gate electrodes 108a and 108b may be within a range from about 0.5 to 5 micrometers. Further, both first and second gate electrodes 108a and 108b may be designed to receive the same voltage from a gate line upon the completion of the TFT. Moreover, an n−ion doping may be performed on the substrate 100, such that a low-density n-type dopant (e.g., phosphorous ions) may be introduced into exposed portions of the active layer 104 which are not overlapped by the first and second gate electrodes 108a and 108b. For example, the dual-gate electrode 108 may function as a mask, such that the active layer 104 may be doped by the n− ions except the portions overlapped by the first and second gate electrodes 108a and 108b. Accordingly, a portion of the active layer 104, which is disposed between the first and second gate electrodes 108a and 108b and doped by the n− ions, may become a first active area C1, and the other portions of the active layer 104, which are also doped by the n−ions, may become second active areas C2.