Crystallographic modification of hard mask properties

A method of forming a layer of interconnect in an integrated circuit comprising the steps of:

• depositing a first layer of interlayer dielectric (ILD) on a lower layer of said integrated circuit above a set of lower alignment marks;
• depositing a first hardmask layer of TaN on said first layer of ILD, said first layer being substantially transparent in a relevant wavelength range;
• forming an upper set of alignment marks;
• patterning said ILD through said hardmask layer to form a set of apertures in said ILD;
• and
• forming a conductive interconnect in said set of apertures;
• in which said hardmask layer is deposited by sputter deposition of Ta in an ambient containing N2 and a carrier gas such that (N2flow)/(N2+carrier flow)>0.5.