Method of manufacturing semiconductor device with triple gate insulating layers

A method of manufacturing a semiconductor device comprising:

• providing a semiconductor substrate in which a first region, a second region and a third region are defined;
• forming a first oxide layer having a relatively thick thickness at the first region compared with the other regions on the entire surface of the substrate;
• forming a dummy gate material layer on the first oxide layer;
• patterning the dummy gate material layer and the first oxide layer to respectively form a first pattern of the first oxide layer and a first dummy gate on the substrate of the first region, and to respectively form a second pattern of the first oxide layer and a second dummy gate on the substrate of the second region;
• forming a gate insulating layer of a second oxide layer and having a first thickness and a gate on the substrate of the third region;
• ion-implanting low concentration impurities into the substrate;
• respectively forming spacers on the sidewalls of the first gate and the first and
• second dummy gates;
• ion-implanting high concentration impurities into the substrate, to form source and drain regions;
• forming an intermediate insulating layer respectively exposing the surfaces of the first gate and the first and second dummy gates and having a smooth surface on the entire surface of the substrate;
• selectively removing the first and the second dummy gates, to form first and second holes respectively exposing the first and second patterns of the first oxide layer;
• forming a third oxide layer on the surfaces of the first and second holes and the intermediate insulating layer;
• depositing a gate material layer on the third oxide layer so as to fill the first and second holes;
• and
• removing the gate material layer and the third oxide layer so as to expose the surface of the intermediate insulating layer, to form a second gate insulating layer consisting of the third oxide layer and the first pattern of the first oxide layer and having a second thickness being thicker than the first thickness on the substrate of the first region, and to form a third gate insulating layer consisting of the third oxide layer and the second pattern of the first oxide layer and having a third thickness being thicker than the first thickness and being thinner than the second thickness on the substrate of the first region.