Method of making layered superlattice material with improved microstructure
AssigneesSymetrix Corporation, Seiko Epson Corporation
InventorsJunichi Karasawa, Vikram Joshi
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AssigneesSymetrix Corporation, Seiko Epson Corporation
InventorsJunichi Karasawa, Vikram Joshi
Estimating the term…
In the manufacture of an integrated circuit, a first electrode (48) is formed on a substrate (28). In a first embodiment, a strontium bismuth tantalate layer (50) and a second electrode (52) are formed on top of the first electrode (48). Prior to the final crystallization anneal, the first electrode (48), the strontium bismuth tantalate layer (50) and the second electrode (52) are patterned. The final crystallization anneal is then performed on the substrate (28). In a second embodiment, a second layer (132) of strontium bismuth tantalate is deposited on top of the strontium bismuth tantalate layer (50) prior to the forming of the second electrode (52) on top of the first and second layers (50), (132). In a third embodiment, a carefully controlled UV baking process is performed on the strontium bismuth tantalate layer (50). In a fourth embodiment, an additional rapid thermal annealing process is performed on a substrate subsequent to the patterning process and prior to the final crystallization annealing process.
A method of fabricating an integrated circuit comprising:
A method of fabricating an integrated circuit comprising:
A method of fabricating an integrated circuit comprising:
A method of fabricating an integrated circuit comprising:
Dependencies are inferred from the claim text.