Seed layer treatment
AssigneeIntel Corporation
InventorsValery M. Dubin, Christopher D. Thomas, Vinay B. Chikarmane
Life of this patent
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Abstract
Seed layer treatment to remove impurities in the seed layer that might lead to the formation of voids in interconnect circuit features. In one embodiment, the seed layer is heated in a reducing environment. In another embodiment, the seed layer is washed with a surfactant that is compatible with a surfactant used when forming the remainder of the circuit feature on the seed layer. Yet another embodiment combines both techniques.
Claims23
A method comprising:
- treating a seed layer of a die by washing in a first solution that includes a first surfactant;
- and
- depositing a conductive material on the seed layer from a second solution that includes a second surfactant, the first surfactant and the second surfactant being non-competing surfactants.
A method comprising heating a die in a reducing environment, the die accommodating a seed layer exposed to the reducing environment forming a seed layer of a die;
- heating said die and exposing said seed layer to a reducing environment;
- after exposing said seed layer to a reducing environment, depositing a conductive material on said seed layer.
A method comprising:
- heating a die with an exposed seed layer in a reducing environment;
- treating the seed layer by washing in a first solution with a first surfactant;
- and
- depositing a conductive material on the seed layer from a second solution with a second surfactant, the first surfactant and the second surfactant being non-competing surfactants.
Dependencies are inferred from the claim text.