Single instruction multiple data processing
AssigneeArm Limited
InventorsDominic Hugo Symes, David James Seal
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Abstract
A data processing system is provided with an instruction (ADD8TO16) that unpacks non-adjacent portions of a data word using sign or zero extension and combines this with a single-instruction-multiple-data type arithmetic operation, such as an add, performed in response to the same instruction. The instruction is well suited to use within systems having a data path (2) including a shifting circuit (6) upstream of an arithmetic circuit (8).
Claims15
Apparatus for data processing, said apparatus comprising:
- (i) a shifting circuit;
- (ii) an arithmetic circuit;
- and
- (iii) an instruction decoder responsive to an instruction to control said shifting circuit and said arithmetic circuit to perform an operation using a first input data word and a second different input data word, wherein said operation yields a result value given by:
- (iv) selecting a plurality of non-adjacent multibit portions of said first input data word to form a plurality of multibit portions each of bit length A;
- (v) optionally shifting said plurality of non-adjacent multibit portions by a common shift amount to shifted bit positions;
- (vi) promoting each of said plurality of non-adjacent multibit portions from said bit length of A to a bit length of B to form a plurality of promoted multibit portions, such that said promoted multibit portions may be abutted to form a promoted data word;
- and
- (vii) performing a plurality of independent arithmetic operations using as input operands respective bit position portions of bit length B from both said promoted data word and said second different input data word to form a result data word.
A method of data processing, said method comprising the steps of decoding and executing an instruction on a first input data word and a second, different input data word that yields a result value given by:
- (i) selecting a plurality of non-adjacent multibit portions of said first input data word to form a plurality of multibit portions of bit length A;
- (ii) optionally shifting said plurality of non-adjacent multibit portions by a common shift amount to shifted bit positions;
- (iii) promoting each of said plurality of non-adjacent multibit portions from said bit length of A to a bit length of B to form a plurality of promoted multibit portions, such that said promoted multibit portions may be abutted to form a promoted data word;
- and
- (iv) performing a plurality of independent arithmetic operations using as input operands respective bit position portions of bit length B from both said promoted data word and said second, different input data word to form a result data word.
Dependencies are inferred from the claim text.