System and method for implementing a micro-stepping delay chain for a delay locked loop
AssigneeInternational Business Machines Corporation
InventorsHarold Pilo, Reid A. Wistort
Life of this patent
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Abstract
A delay locked loop for use in an integrated circuit device includes a coarse delay chain in series with a micro-stepped delay chain. The coarse delay chain includes a plurality of coarse delay units configured for selectively providing a coarse delay with respect to an input clock signal, and the micro-stepped delay chain is configured for selectively providing a fine delay adjustment with respect to the input clock signal. The micro-stepped delay chain further includes a plurality of parallel signal paths, wherein one or more of the parallel signal paths are capacitively loaded so as to provide the fine delay adjustment.
Claims19
A method for implementing delay locked loop in an integrated circuit device, the method comprising:
- configuring a coarse delay chain in series with a micro-stepped delay chain;
- said coarse delay chain including a plurality of variable coarse delay units configured for selectively providing a coarse delay with respect to an input clock signal, and said micro-stepped delay chain configured for selectively providing a fine delay adjustment with respect to said input clock signal;
- and
- configuring a plurality of parallel signal paths within said micro-stepped delay chain, wherein one or more of said parallel signal paths are capacitively loaded so as to provide said fine delay adjustment.
A method for implementing a micro-stepped delay chain for use in a delay locked loop, the method comprising:
- coupling a plurality of parallel signal paths to a common input;
- a first of said plurality of parallel signal paths comprising a single coarse delay unit;
- a second of said plurality of parallel signal paths comprising a pair of coarse delay units;
- and
- the remainder of said plurality of parallel signal paths each comprising a single coarse delay unit having an intermediate node thereof loaded with a stepped value of capacitance with respect to one another;
- wherein a signal propagated through any of said remainder of said plurality of parallel signal paths has a delay associated therewith that represents a stepped valued of delay between the delay provided by said single coarse delay unit and the delay provided by said pair of coarse delay units.
Dependencies are inferred from the claim text.