Data converter and method thereof
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsKaoru Yokota, Motoji Ohmori, Makoto Tatebayashi, Makoto Usui
Life of this patent
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Abstract
A data converter (1) capable of reducing a size of the total implementation in a device is a processing apparatus that performs secret converting processing predetermined to input data with 64 bits, the data converter including a finite field polynomial cubing unit (10), data integrating units (11a) to (11d), (12) and (13), a first converter (14), a second converter (15), a data splitting unit (16), and a data integrating unit (17). The finite field polynomial cubing unit (10) performs cubing, on the 32 bits data, in the polynomial residue class ring with a value in the finite field GF (28) as a coefficient and respectively outputs data with 32 bits.
Claims16
A data converter comprising:
- a splitting unit operable to split input data into a plurality of data blocks;
- a conversion performing unit operable to perform conversion on each one of the plurality of data blocks, the conversion being based on an exponentiation to a predetermined exponent in a polynomial residue class ring with a value in a finite field GF (2n), the n being a natural number, as a coefficient;
- and
- an output data generating unit operable to generate output data based on the plurality of data blocks converted by the conversion performing unit,
- wherein the predetermined exponent is a value that is 3 or larger and other than 2m, the m being an integer which is 1 or larger.
A data conversion method comprising:
- splitting input data into a plurality of data blocks;
- performing conversion on each one of the plurality of data blocks, the conversion being based on an exponentiation by a predetermined exponent in a polynomial residue class ring with a value in a finite field GF (2n), the n being a natural number, as a coefficient;
- and
- generating output data based on the plurality of data blocks converted by the conversion performance,
- wherein the predetermined exponent is a value that is 3 or larger and except 2m, the m being an integer which is 1 or larger.
An integrated circuit comprising:
- a finite field multiplying unit operable to perform multiplication in a finite field GF (2n), the n being a natural number;
- an error-correction coding unit operable to perform error-correction coding on input data by performing multiplication in the finite field GF (2n) using the finite field multiplying unit;
- a splitting unit operable to split the input data into a plurality of data blocks;
- a conversion performing unit operable to perform conversion on each one of the plurality of data blocks, the conversion being based on an exponentiation to a predetermined exponent in a polynomial residue class ring with a value in the finite field GF (2n) as a coefficient;
- and
- generating output data unit based on the plurality of data blocks converted by the conversion performing unit,
- wherein the predetermined exponent is a value that is 3 or larger and other than 2m, the m being an integer that is 1 or larger.
A program that causes a computer to execute:
- splitting input data into a plurality of data blocks;
- performing conversion on each one of the plurality of data blocks using a finite field multiplying unit operable to perform multiplication in a finite field GF (2n), the n being a natural number, the conversion being based on an exponentiation to a predetermined exponent in a polynomial residue class ring with a value in the finite field GF (2n) as a coefficient;
- and
- generating output data based on the plurality of data blocks converted by the conversion performance,
- wherein the predetermined exponent is a value that is 3 or larger and other than 2m, the m being an integer which is 1 or larger.
Dependencies are inferred from the claim text.