Rail stack array of charge storage devices and method of making same

A monolithic, three dimensional array of charge storage devices, comprising a plurality of device levels monolithically formed above a substrate, wherein:

• each of the plurality of device levels comprises a plurality of spaced apart semiconductor active regions and a plurality of spaced apart rails;
• the plurality of active regions are disposed at a first height;
• the plurality of rails are disposed at a second height different than the first height;
• and
• wherein the active regions comprise first portions of the charge storage devices and the rails comprise second portions of the charge storage devices.

A method of making a monolithic three dimensional array of charge storage transistors disposed above a substrate, comprising:

• a) forming a first device level of charge storage transistors, the first device level comprising:
• i) a plurality of spaced apart first rails extending in a first direction;
• and
• ii) a plurality of spaced apart second rails formed over the first rails extending in a second direction different from the first direction;
• wherein the first rails comprise first portions of the charge storage transistors and the second rails comprise second portions of the charge storage transistors;
• and
• b) monolithically forming a second device level of charge storage transistors above the first device level.

An integrated circuit, comprising:

• a three-dimensional memory array having more than one memory level of memory cells, each memory level of said integrated circuit comprising:
• a plurality of rails on an insulating layer above the substrate, said rails running in a first direction, said rails comprising a lightly-doped semiconductor region disposed between heavily-doped semiconductor regions;
• a charge storage film on the rails;
• a plurality of word lines on the charge storage film, said word lines running in a second direction different than the first direction;
• and
• an interlevel insulating layer above the word lines.

A method for manufacturing an integrated circuit comprising a three-dimensional memory array having more than one memory level of memory cells, the method comprising:

• forming a plurality of rails on an insulating layer above a substrate, said rails running in a first direction;
• forming heavily-doped semiconductor regions in the rails such that a lightly-doped semiconductor region is disposed between the heavily-doped semiconductor regions;
• forming a charge storage film on the rails;
• forming a plurality of word lines on the charge storage film, said word lines running in a second direction different than the first direction;
• forming an interlevel insulating layer above the word lines;
• and monolithically forming a second device level over the interlevel insulating layer.