Method and apparatus for processing control using a multiple redundant processor control system

A synchronization system for synchronizing a plurality of main processor modules, said main processor modules being configured to process control information related to control elements, said synchronization system comprising:

• a communication system configured to couple each of said plurality of main processor modules to all others of said plurality of main processor modules;
• and
• a plurality of timers, each of said plurality of timers being coupled to a corresponding one of said plurality of main processor modules;
• wherein each of said plurality of main processor modules is configured to send a rendezvous signal to all others of said plurality of main processor modules in response to an indication of an elapsed time provided by a corresponding one of said plurality of timers.

A synchronization system for synchronizing a plurality of main processors comprising:

• means for sending from a first of said plurality of main processors, at a first time and in response to a first time reference, a first rendezvous signal to a second of said plurality of main processors;
• means for sending from said second of said plurality of main processors, at a second time and in response to a second time reference, a second rendezvous signal to said first of said plurality of main processors;
• and
• means for initiating, after said first rendezvous signal is received by said second of said plurality of main processors and said second rendezvous signal is received by said first of said plurality of main processors, substantially simultaneous scanning of control information by said first and second of said plurality of main processors.

A method for identifying a fault condition in a synchronization system comprising:

• sending, at a first time and in response to a first time reference of a first main processor, a first rendezvous signal to a second main processor and a third main processor;
• sending, at a second time and in response to a second time reference of said second main processor, a second rendezvous signal to said first main processor and said third main processor;
• sending, at a third time and in response to a third time reference of said third main processor, a third rendezvous signal to said first and said second main processors;
• receiving said second rendezvous signal and said third rendezvous signal at said first main processor at a fourth time and a fifth time, respectively;
• and
• identifying a fault condition of one of said at least three main processors based upon differences between said first time and said fourth time and between said first time and said fifth time.