Microprocessor and method for utilizing disparity between bus clock and core clock frequencies to prioritize cache line fill bus access requests

A data cache, in a microprocessor coupled to a system memory by a bus, the microprocessor core logic operating according to a core clock, the bus operating according to a bus clock, the data cache comprising:

• a request queue, for storing a plurality of requests to fill a cache line from the system memory on the bus, said requests comprising a plurality of types;
• request accumulation logic, coupled to said request queue, for storing said plurality of requests into said request queue in an order received during core clock cycles;
• prioritization logic, coupled to said request queue, for prioritizing said plurality of requests based on said plurality of types during a core clock cycle just prior to a next bus clock cycle;
• and
• bus request issue logic, coupled to said request queue, for removing from said request queue a highest priority of said plurality of requests prioritized by said prioritization logic for issuance on the bus, wherein said prioritization logic prioritizes requests causing a pipeline stall in the microprocessor as highest priority of said plurality of requests.

A microprocessor, comprising:

• a bus clock input, for receiving a bus clock signal, said bus clock signal having a first frequency for controlling operation of a bus coupling the microprocessor to a system memory;
• a core clock signal, having a second frequency, for controlling operation of core logic in the microprocessor, said second frequency being a multiple of said first frequency;
• a data cache, coupled to receive said core clock signal, for generating requests to read a cache line on said bus, said requests each having a request type;
• and
• control logic, coupled to said data cache, for accumulating said requests at said second frequency, for prioritizing said accumulated requests based on said request type at said first frequency, and for issuing a highest priority one of said requests on said bus after said prioritizing, wherein said request type includes at least two of the following request types:
• a blocking request type, a non-blocking page table data request type, a non-block store allocation request type wherein said blocking request type is highest priority, and a non-blocking prefetch request type.

A method for a microprocessor to transfer cache lines from a system memory on a bus coupling the microprocessor and system memory, the bus operating at a bus clock frequency and the microprocessor core logic operating at a core clock frequency, the method comprising:

• determining during a core clock cycle whether said core clock cycle is occurring just prior to a next bus clock cycle, wherein the core clock frequency is a multiple of the bus clock frequency;
• prioritizing during said core clock cycle a plurality of bus requests accumulated during previous core clock cycles according to request type, if said determining is true;
• and
• issuing during said next bus clock cycle a highest priority one of said plurality of bus requests on the bus after said prioritizing.