System and method for timing recovery in a discrete multi-tone system

A method for timing recovery at the receiver in a discrete multi-tone (DMT) communications system comprising:

• receiving a pilot tone generated and transmitted by an associated far-end transmission unit along with other signal streams at a particular receiver;
• converting the plurality of received signals through an analog to digital converter (ADC) to create a digital signal stream;
• detecting a cyclic prefix in the received digital signal stream;
• zeroing out the received digital signal stream from the input to a timing recovery circuit while the cyclic prefix is present in the received signal stream to create a frequency correction signal;
• and
• using the frequency correction signal to modify the ADC sampling timing.

A method for timing recovery at the receiver in a discrete multi-tone (DMT) communications system comprising:

• receiving a standard pilot tone generated and transmitted by an associated far-end transmission unit along with other signal streams at a particular receiver;
• converting the plurality of received signals through an analog to digital converter (ADC) to create a digital signal stream;
• detecting a cyclic prefix in the digital signal stream;
• using the digital signal stream with the cyclic prefix portion removed to generate an average pilot phase error using a discrete Fourier transform (DFT);
• applying the average pilot phase error to the input of a timing recovery circuit to create a frequency correction signal;
• and
• using the frequency correction signal to modify the sampling time of the ADC.

A system for timing recovery in a discrete multi-tone communications system comprising:

• an analog to digital converter (ADC) configured to create a digital representation of the received signal;
• a timing recovery circuit in communication with the ADC configured to receive the received signal and to apply a control signal to the ADC, wherein the received signal sample stream is synchronized for further processing at a rate compatible with that of a source transmission.;
• and
• a symbol synchronizer in communication with the ADC configured to determine when the data stream contains a cyclic prefix, the symbol synchronizer further configured to remove the received signal from the timing recovery circuit input when the cyclic prefix is present.

A system for timing recovery in a discrete multi-tone communications system comprising:

• an analog to digital converter (ADC) configured to create a digital representation of the received signal;
• an equalizer in communication with the ADC, the equalizer configured to perform a time-domain equalization on the received signal;
• a timing recovery circuit in communication with the ADC and the equalizer configured to receive the received signal and to apply a control signal to the ADC, wherein the received signal sample stream is synchronized for further processing at a rate compatible with that of a source transmission;
• and
• a symbol synchronizer in communication with the ADC configured to determine when the signal stream contains a cyclic prefix, the symbol synchronizer further configured to remove the time-domain equalized signal from the timing recovery circuit input when the cyclic prefix is present.

A system for timing recovery in a discrete multi-tone communications system comprising:

• an analog to digital converter (ADC) configured to create a digital representation of the received signal;
• an equalizer in communication with the ADC, the equalizer configured to perform a time-domain equalization on the received signal;
• a symbol synchronizer in communication with the ADC configured to remove a cyclic prefix from the signal sample stream;
• a discrete Fourier transform (DFT) in communication with both the equalizer and the symbol synchronizer, the DFT configured to convert the time-equalized received signal and to generate a pilot tone phase error estimate signal;
• a timing recovery circuit in communication with the ADC and the DFT configured to receive the pilot tone phase error estimate and to apply a control signal to the ADC, wherein the received signal sample stream is synchronized for further processing at a rate compatible with that of a source transmission.

A system for timing recovery at the receiver in a discrete multi-tone (DMT) communications system comprising:

• means for receiving a standard pilot tone and far-end signal from an associated far-end transmission;
• means for converting the plurality of received signals from analog to digital signals;
• means for detecting a cyclic prefix in the received far-end signal;
• means for removing the cyclic prefix in the received far-end signal;
• means for generating an average pilot phase error using a discrete Fourier transform (DFT);
• and
• means for applying the average pilot phase error to the input of a timing recovery circuit to create a frequency correction signal;
• and
• means for using the frequency correction signal to modify the sampling rate of the analog to digital conversion.

A system for timing recovery at the receiver in a discrete multi-tone (DMT) communications system comprising:

• means for receiving a standard pilot tone along with a plurality of signals at this particular receiver from a far-end signal;
• means for converting the plurality of signals from analog to digital signals;
• means for performing a time-domain equalization on the far-end signal;
• means for detecting a cyclic prefix in the far-end signal;
• means for zeroing out the equalized digital signal from the input to a phase locked-loop while the cyclic prefix is present in the received signal to create frequency correction signal;
• and
• means for using the frequency correction signal to modify the sampling rate of the analog to digital conversion.

A system for timing recovery at the receiver in a discrete multi-tone (DMT) communications system comprising:

• means for receiving a far-end signal along with a plurality of signals at the receiver;
• means for converting the plurality of received signals from an analog to a digital format;
• means for detecting a cyclic prefix in the far-end signal;
• means for zeroing out the far-end signal when the cyclic prefix is present from the input to a timing recovery circuit;
• and
• means for using the phase locked-loop output to modify the sampling rate of the analog to digital conversion.