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US 6,982,722 B1Granted
System for programmable dithering of video data
AssigneeNVIDIA Corporation
InventorsJonah M. Alben, Stephen Lew
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AssigneeNVIDIA Corporation
InventorsJonah M. Alben, Stephen Lew
Estimating the term…
A programmable system for dithering video data. The system is operable in at least two user-selectable modes which can include a small kernel mode and a large kernel mode. In some embodiments, the system is operable in at least one mode in which it applies two or more kernels (each from a different kernel sequence) to each block of video words. Each kernel sequence repeats after a programmable number of the blocks (e.g., a programmable number of frames containing the blocks) have been dithered. The period of repetition is preferably programmable independently for each kernel sequence. The system preferably includes a frame counter for each kernel sequence. Each counter generates an interrupt when the number of frames of data dithered by kernels of the sequence has reached a predetermined value. In response to the interrupt, software can change the kernel sequence being applied. Typically, the system performs both truncation and dithering on words of video data. For example, some embodiments produce dithered 6-bit color components in response to 8-bit input color component words. Preferably, the inventive system is optionally operable in either a normal mode (in which dithering is applied to all pixels in accordance with the invention) or in an anti-flicker mode. Another aspect of the invention is a computer system in which the dithering system is implemented as a subsystem of a pipelined graphics processor or display device. Another aspect of the invention is a display device that includes an embodiment of the dithering system.
A system for dithering video data, wherein the system is operable in at least one mode in which it applies at least a first kernel sequence and a second kernel sequence to each set of a sequence of sets of input video bits, repeats application of the first kernel sequence after a first number of the sets have been dithered in response to said first kernel sequence, and repeats application of the second kernel sequence after a second number of the sets have been dithered in response to said second kernel sequence, wherein each said kernel sequence is a sequence of kernels consisting of dither bits.
A pipelined graphics processor, including circuitry for dithering video data, wherein the circuitry is operable in at least one mode in which it applies at least a first kernel sequence and a second kernel sequence to each set of a sequence of sets of input video bits, repeats application of the first kernel sequence after a first number of the sets have been dithered in response to said first kernel sequence, and repeats application of the second kernel sequence after a second number of the sets have been dithered in response to said second kernel sequence, wherein each said kernel sequence is a sequence of kernels consisting of dither bits.
A display device, including circuitry for dithering video data, wherein the circuitry is operable in at least one mode in which it applies at least a first kernel sequence and a second kernel sequence to each set of a sequence of sets of input video bits, repeats application of the first kernel sequence after a first number of the sets have been dithered in response to said first kernel sequence, and repeats application of the second kernel sequence after a second number of the sets have been dithered in response to said second kernel sequence, wherein each said kernel sequence is a sequence of kernels consisting of dither bits.
A computer system, including:
Dependencies are inferred from the claim text.