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US 6,982,476 B2Granted
Integrated circuit feature layout for improved chemical mechanical polishing
AssigneeMatrix Semiconductor, Inc.
InventorsJames M. Cleeves, Michael A. Vyvoda
Life of this patent
Estimating the term…
Abstract
The present invention is a level of an integrated circuit. The level of integrated circuit has a first area having a plurality of features having a first density and the level of the integrated circuit has a second area adjacent to the first area wherein the second area has a plurality of dummy features having a density substantially similar to the first density.
Claims7
A level of an integrated circuit comprising:
- a core area having a 25 μm2 area, said core area having a first density of features wherein said first density of features is the total area of features in the core area divided by the total core area;
- and
- a peripheral area adjacent to said core area and having a 25 μm2 area, said peripheral area having a second density of features wherein said second density is the total area of features in the peripheral area divided by the total peripheral area, wherein said second density is substantially similar to said first density.
A level of an integrated circuit comprising:
- a first area having a first plurality of active features having a first active feature density in a 25 μm2 area, wherein said first active feature density is the total area of active features in said first area divided by the total area of said first area;
- and
- a second area 25 μm2 area adjacent to said first area 25 μm2 area, said second area having a plurality of dummy features having a second feature density in a 25 μm2 area substantially similar to said first active feature density.
Dependencies are inferred from the claim text.