US 6,981,167 B2 · Programmable controller with sub-phase clocking scheme

Abstract

A parallel processor with a built-in sub-phase clocking scheme is provided to execute sequentially executed programmable logic controller (PLC) programs in a parallel method. A translator program will translate the PLC logic design from a coding language into Electronic Design Interchange Format and that will be eventually converted to a hardware or software embodiment of the logic. The processor provides a plurality of sub-phase clock periods. The translator assigns to the same sub-phase period program elements that process their tasks in the same range of time. The elements are grouped into sub-phase so that logic elements are performed lock-step to ensure that downstream element are performed at a time when they have valid values at their inputs. The processor consequently avoids race conditions in the system and allows the parallel execution speedup of programs written for a sequential machine such as a PLC.

Claims20

Dependent claims

A system for automatically alleviating processor race conditions, the system comprising:

a sub-phase clocking mechanism for dividing a circuit clock into a plurality of sub-phases, said sub-phase clocking mechanism adapted for use in a programmable logic controller;
and
a translator for (i) translating programmable logic controller program elements from a coding language into Electronic Design Interchange Format, (ii) classifying each program element according to specified ranges of time required for the program element to perform its tasks, and (iii) assigning program elements within each range for time to a corresponding clock sub-phase.

Dependencies are inferred from the claim text.

Programmable controller with sub-phase clocking scheme

Life of this patent

Programmable controller with sub-phase clocking scheme

Life of this patent

Abstract

Claims20