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US 6,980,140 B1Granted
Flash ADC receiver with reduced errors
AssigneeNortel Networks Limited
InventorsAndy Rowland, Tom Luk, Sevgui Hadjihassan
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Abstract
Symbol decoding errors at a receiver utilising a flash analog to digital converter (ADC) can be reduced by adjusting a reference voltage level of the ADC where a decoding error rate at the reference voltage level exceeds a threshold.
Claims16
A receiver comprising:
- a flash analog to digital converter (ADC);
- a symbol decoder, which receives input from said ADC and operates on groups of bits of a fixed bit length, each group of bits comprising a target bit and bits adjacent in time to said target bit, said bits adjacent in time to said target bit being assumed to affect a voltage of said target bit before decoding due to inter-symbol interference;
- a link quality indicator, which receives input from said symbol decoder and generates link quality indications therefrom;
- and
- reference voltage adjuster, which receives input from said ADC and the link quality indications from the link quality indicator and, responsive thereto outputs to a control input to said ADC for selectively adjusting one or more reference voltages of said ADC.
2 more elements
A receiver comprising:
- a flash analog to digital converter (ADC);
- decoding means responsive to said ADC to decode symbols, said decoding means operating on groups of bits of a fixed bit length, each group of bits comprising a target bit and bits adjacent in time to said target bit, said bits adjacent in time to said target bit being assumed to affect a voltage of said target bit before decoding due to inter-symbol interference;
- link quality detecting means responsive to said decoding means to detect symbol decoding errors;
- and
- a channel estimation block responsive to said ADC and said symbol decoding errors for adjusting reference voltages of said ADC.
2 more elements
In a receiver utilising a flash analog to digital converter (ADC), a method of improving link quality comprising:
- adjusting a reference voltage for a voltage slicing level of said ADC when a decoding error rate at said voltage slicing level exceeds said threshold wherein
- decoding symbols on said link and determining said decoding error rate at said voltage slicing level, said decoding comprising operating on groups of bits of a fixed bit length, each group of bits comprising a target bit and bits adjacent in time to said target bit, said bits adjacent in time to said target bit being assumed to affect a voltage of said target bit before decoding due to inter-symbol interference.
Dependencies are inferred from the claim text.