Dummy delay line based DLL and method for clocking in pipeline ADC

A pipeline ADC comprising:

• (a) a sample and hold amplifier that samples an input to the pipeline ADC followed by a first pipeline stage of the pipeline ADC, wherein each of a plurality of pipeline stages samples the previous pipeline stage during a sample clock phase and produces a residue signal through a gain amplifier of the pipeline stage during a hold clock phase;
• (b) a delay locked loop clock generation circuit including
• i. a delay locked loop circuit including a delay line including a plurality of serially connected delay stages, a first delay stage being connected to receive a first clock signal, each of the delay stages having a delay control input connected to receive a delay control signal, various tap points of the delay line being coupled to inputs of a clock logic circuit operating on various tap point signals conducted by the various tap points, respectively, to generate a plurality of clock signals, a phase detector having a first input connected to receive the first clock signal, a second input connected to an output of a final delay stage of the delay line, and an output, a charge pump circuit having an input connected to the output of the phase detector and an output producing the delay control signal;
• (c) a dummy delay line including a delay line;
• and
• (d) a watchdog circuit having a plurality of inputs coupled to tap points of the dummy delay line.

A pipeline ADC comprising:

• (a) a sample and hold amplifier that samples an input to the pipeline ADC followed by a first pipeline stage of the pipeline ADC, wherein each of a plurality of pipeline stages samples the previous pipeline stage during a sample clock phase and produces a residue signal through a gain amplifier of the pipeline stage during a hold clock phase;
• (b) a delay locked loop clock generation circuit including
• (1) a delay locked loop circuit including
• i. a delay line including a plurality of serially connected delay stages, a first delay stage being connected to receive a first clock signal, each of the delay stages having a delay control input connected to receive a delay control signal, various tap points of the delay line being coupled to inputs of a clock logic circuit operating on various tap point signals conducted by the various tap points, respectively, to generate a plurality of clock signals,
• ii. a phase detector having a first input connected to receive the first clock signal, a second input connected to an output of a final delay stage of the delay line, and an output, and
• iii. a charge pump circuit having an input connected to the output of the phase detector and an output producing the delay control signal;
• (2) a dummy delay line including a delay line including a plurality of serially connected to dummy delay stages that are matched to corresponding delay stages of the delay line, a first dummy delay stage being connected to receive a second clock signal which is inverted with respect to the first clock signal, each of the dummy delay stages having a delay control input connected to receive the delay control signal;
• and
• (3) a watchdog circuit having a plurality of inputs coupled to various tap points of the dummy delay line to generate a first control signal coupled to the phase detector and a second control signal coupled to the charge pump circuit,
• wherein corresponding delay stages and dummy delay stages are located physically close to each other in a substrate of an integrated circuit chip and co-act to cancel noise injected into the substrate as a result of switching of the delay stages.

A method of reducing substrate noise in a delay locked loop circuit, comprising:

• (a) providing a delay locked loop circuit including
• i. a delay line including a plurality of serially connected delay stages, a first delay stage being the state connected to receive a first clock signal, each of the delay stages having a delay control input connected to receive a delay control signal, various tap points of the delay line being coupled to inputs of a clock logic circuit operating on various tap point signals conducted by the various tap points, respectively, to generate a plurality of clock signals,
• ii. a phase detector having a first input connected to receive the first clock signal, a second input connected to an output of a final delay stage of the delay line, and an output, and
• iii. a delay control circuit having an input connected to the output of the phase detector and an output producing the delay control signal, wherein switching of the delay stages causes parasitic coupling of noise between outputs of the delay stages and a substrate of an integrated circuit in which the delay locked loop circuit is formed;
• and
• (b) canceling the parasiticly coupled noise by synchronously coupling opposite-polarity noise into the substrate,
• including performing step (b) by providing a dummy delay line including a delay line including a plurality of serially connected dummy delay stages that are matched to corresponding delay stages of the delay line, respectively, a first dummy delay stage being connected to receive a second clock signal which is inverted with respect to the first clock signal, each of the dummy delay stages having a delay control input connected to receive the delay control signal such that corresponding delay stages and dummy stages are located physically close to each other in the substrate.

A method of reducing substrate noise in a pipeline ADC, comprising:

• (a) providing a sample and hold amplifier that samples an input to the pipeline ADC followed by a first pipeline stage of the pipeline ADC, wherein each of a plurality of pipeline stages samples the previous pipeline stage during a sample clock phase and produces a residue signal through a gain amplifier of the pipeline stage during a hold clock phase;
• (b) providing a delay locked loop circuit including
• i. a delay line including a plurality of serially connected delay stages, a first delay stage being the state connected to receive a first clock signal, each of the delay stages having a delay control input connected to receive a delay control signal, various tap points of the delay line being coupled to inputs of a clock logic circuit operating on various tap point signals conducted by the various tap points, respectively, to generate a plurality of clock signals,
• ii. a phase detector having a first input connected to receive the first clock signal, a second input connected to an output of a final delay stage of the delay line, and an output, and
• iii. a delay control circuit having an input connected to the output of the phase detector and an output producing the delay control signal, wherein switching of the delay stages causes parasitic coupling of noise between outputs of the delay stages and a substrate of an integrated circuit in which the delay locked loop circuit is formed;
• and
• (c) canceling the parasiticly coupled noise by synchronously coupling opposite-polarity noise into the substrate,
• including performing step (c) by providing a dummy delay line including a delay line including a plurality of serially connected dummy delay stages that are matched to corresponding delay stages of the delay line, respectively, a first dummy delay stage being connected to receive a second clock signal which is inverted with respect to the first clock signal, each of the dummy delay stages having a delay control input connected to receive the delay control signal such that corresponding delay stages and dummy stages are located physically close to each other in the substrate.