Rational frequency synthesizers

A method of phase-lock loop (PLL) frequency synthesis, the method comprising:

• receiving a reference signal having a reference frequency Fref in a frequency ratio generator FRG;
• generating through a voltage controlled oscillator (VCO) a VCO output signal having a frequency Fosc;
• coupling said VCO output signal to a first input of a phase detector;
• filtering an output of said phase detector to obtain a filtered signal for coupling said filtered signal to said VCO;
• coupling said reference signal from said FRG to a second input of said phase detector, said FRG generating a comparison frequency signal G1 whose dominant frequency component Fc is a desired frequency Fosc based on a fraction expansion of a ratio P/Q of said desired frequency Fosc and said reference frequency Fref,
• wherein P and Q are integer numbers, said ratio P/Q being realized according to a mathematical expression 1±1/p1±1/p2± . . . 1/pn, or realized according to a mathematical expression 1±1/q1·{1±1/q2·[ . . . (1±1/qm))) . . . ]}, or realized according to a combination of said mathematical expressions,
• wherein n, m and coefficients p1, p2, . . . , pn, q1, q2, . . . , qm are positive integer numbers, and
• whereby all additions in said mathematical expressions are realized by upper side-band SSB mixing, all subtractions are realized by lower-side-band SSB mixing, and all fractions 1/p1 through 1/pn and 1/q1 through 1/qm are realized by frequency division.

A method of Frequency Ratio Generation (FRG) frequency translation, the method comprising:

• receiving an input signal having a frequency Fin;
• generating a signal whose dominant frequency component Fg is equal to a ratio P/Q multiplied by said frequency Fin,
• wherein P and Q are integer numbers,
• said ratio P/Q being realized according to a mathematical expression 1±1/p1±1/p2± . . . 1/pn, or realized according to a mathematical expression 1±1/q1·{1±1/q2·[ . . . (1±1/qm))) . . . ]}, or realized according to a combination of said mathematical expressions;
• wherein n, m and coefficients p1, p2, . . . pn, q1, q2, . . . , qm are positive integer numbers, and
• whereby all additions in said mathematical expressions are realized by upper side-band SSB mixing, all subtractions are realized by lower-side-band SSB mixing and all fractions 1/p1 through 1/pn and 1/q1 through 1/qm are realized by frequency division.

A phase-lock loop (PLL) frequency synthesizer device, comprising:

• a Frequency Ratio Generator (FRG) frequency translator, comprising:
• an input signal having a frequency Fin;
• and
• an output signal having a dominant frequency Fg=P/Q Fin, P/Q being a ratio of two positive integers equal to one of a first fraction expansion 1±1/p1±1/p2± . . . 1/pn, a second fraction expansion 1±1/q1·{1±1/q2·[ . . . (1±1/qm))) . . . ]}, or a mathematical expression which is a combination of said first and second fraction expansions, m, n and coefficients p1, p2, . . . , pn, q1, q2, . . . , qm being positive integer numbers, all additions being realized by using an upper side-band SSB mixer (USB), all subtractions by a lower-side-band SSB mixer (LSB) and all the fractions 1/p1 through 1/pn and 1/q1 through 1/qm by a frequency divider;
• an input reference signal having a reference frequency Fref;
• a voltage controlled oscillator (VCO) output signal having a frequency Fo coupled to said input of said FRG to produce said output signal at an output of said FRG having a dominant frequency Fg=R/S·Fo, R/S being a ratio of two positive integers,
• wherein said output signal having said dominant frequency Fg is phase locked with said input reference signal having a reference frequency Fref through a phase detector to generate a phase detector output such that said frequency Fg becomes substantially equal to said reference frequency Fref satisfying the relationship Fo=S/R·Fref;
• a loop filter for filtering said phase detector output to generate a loop filter output;
• and
• a VCO output signal generated by transmitting said loop filter output to a tuning input of said VCO.

A method of phase-lock loop (PLL) frequency synthesis using a Frequency Ratio Generator (FRG) frequency translation, the method comprising:

• receiving an input signal having a frequency Fin at an input of said FRG;
• producing an output signal at an output of said FRG having a dominant frequency Fg=P/Q·Fin, P/Q being a ratio of two positive integers equal to one of a first fraction expansion 1±1/p1±1/p2± . . . 1/pn, a second fraction expansion 1±1/q1·{1±1/q2·[ . . . (1±1/qm))) . . . ]}, or a mathematical expression which is a combination of said first and second fraction expansions, m, n and coefficients p1, p2, . . . , pn, q1, q2, . . . , qm being positive integer numbers, realizing all additions by upper side-band SSB mixing (USB), all subtractions by lower-side-band SSB mixing (LSB) and all the fractions 1/p1 through 1/pn and 1/q1 through 1/qm by frequency division;
• and
• receiving an input reference signal having a reference frequency Fref;
• generating through a voltage controlled oscillator (VCO) a VCO output signal having a frequency Fo and coupling it to said input of said FRG, thereby producing at said output of said FRG a translated output signal having a dominant frequency Fg=R/S·Fo, R/S being a ratio of two positive integers;
• phase locking said translated output signal having said dominant frequency Fg with said input reference signal having a reference frequency Fref through a phase detector, generating a phase detector output such that said frequency Fg becomes substantially equal to said reference frequency Fref satisfying the relationship Fo=S/R·Fref;
• filtering said phase detector output through a loop filter generating a loop filter output;
• and
• transmitting said loop filter output to a tuning input of said VCO producing said VCO output signal.