Algorithm mapping, specialized instructions and architecture features for smart memory computing
OwnerShine C. Chunginventor
Life of this patent
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Abstract
A smart memory computing system that uses smart memory for massive data storage as well as for massive parallel execution is disclosed. The data stored in the smart memory can be accessed just like the conventional main memory, but the smart memory also has many execution units to process data in situ. The smart memory computing system offers improved performance and reduced costs for those programs having massive data-level parallelism. This smart memory computing system is able to take advantage of data-level parallelism to improve execution speed by, for example, use of inventive aspects such as algorithm mapping, compiler techniques, architecture features, and specialized instruction sets.
Claims25
A smart memory integrated circuit comprises:
- an instruction memory;
- a plurality of data memory blocks that store data for general storage;
- a plurality of multi-port register files coupled to said data memory blocks to provide storage of temporary data;
- an input cross-bar switch coupled to said register files;
- a plurality of execution units coupled to said input cross-bar switch and thus to said register files and said data memory blocks, said execution units execute instructions stored in said instruction memory;
- and
- an output cross-bar switch coupled from said execution units to said register files,
- wherein said instruction memory supplies the same instruction to said execution units operating concurrently.
Dependencies are inferred from the claim text.