Controlled frequency power factor correction circuit and method
AssigneeJPMorgan Chase Bank, N.A.
InventorJoel Turchi
Life of this patent
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Abstract
A power factor correction (PFC) circuit (10) includes a latch (16) having an output that initiates a coil current (ICOIL) in response to a transition edge of a clock signal (CLOCK) to generate a PFC signal (VOUT). An input receives a control signal (TERM). A current modulation circuit (14) has a first input (36) coupled for receiving the PFC signal to establish a charging time (TCH) of the coil current. A second input senses the coil current to establish a duty cycle of the coil current over a period of the clock signal, and an output (38) provides the control signal as a function of the charging time and the duty cycle.
Claims19
A power factor correction circuit, comprising:
- a first latch having an output for initiating a coil current in response to a transition edge of a clock signal to generate a PFC signal, and an input for receiving a control signal;
- a current modulation circuit having a first input coupled for receiving the PFC signal to establish a charging time of the coil current, a second input coupled for sensing the coil current to establish a duty cycle of the coil current over a period of the clock signal, and an output for providing the control signal as a function of the charging time and the duty cycle;
- and
- a current sensor having an input coupled for sensing the coil current and an output for providing a sense signal, the current sensor including a first amplifier having a first input coupled to the input of the current sensor and a second input for establishing a threshold level of the coil current, and the current sensor also including a second latch having a first input coupled to the output of the first latch, a second input coupled to an output of the first amplifier and an output coupled to the second input of the current modulation circuit for generating the sense signal as a first logic state on the transition edge of the clock signal and as a second logic state when the coil current falls below the threshold level.
A method of correcting a power factor, comprising the steps of:
- initiating a coil current at the beginning of a clock period to generate a power factor corrected signal;
- sensing both a charging portion of the coil current and a discharging portion of the coil current to determine a duty cycle of the coil current over the clock period;
- and
- terminating a charging portion of the coil current with a control signal that is a function of the PFC signal and the duty cycle.
An integrated power factor correction circuit, comprising:
- a driver circuit having a first input for receiving clock pulses to initiate a coil current, a second input for receiving a control signal to terminate a charging portion of the coil current, and an output for generating a PFC signal with the coil current;
- and
- a modulation circuit having a first input coupled for sensing the PFC signal to set an amplitude of the coil current, a second input for monitoring the coil current over a period of the clock pulses to produce a duty cycle signal, and an output for providing the control signal as a function of the amplitude and the duty cycle signal.
Dependencies are inferred from the claim text.