Memory trouble relief circuit
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorNoriko Mizukoshi
Life of this patent
Estimating the term…
Abstract
When a redundancy circuit is provided to relieve the inferiority of a semiconductor storage device, and then, the semiconductor storage device has no defect, power is inconveniently supplied even to the unused redundancy circuit to generate unnecessary leakage current. A self-diagnosis circuit for a semiconductor storage device is provided to perform the self-diagnosis of the semiconductor storage device upon turning on a power source. Power (2) is supplied to a redundancy circuit part and power (1) is supplied to a circuit part except the redundancy circuit part. When the semiconductor storage device has no defect as a result of the self-diagnosis, a control for turning off the power (2) of the redundancy circuit part is performed.
Claims6
A memory trouble relief circuit for relieving a failure of a memory of a semiconductor integrated circuit having the memory, the memory trouble relief circuit comprising:
- a self-diagnosis circuit, which diagnoses the memory and outputs a diagnosed result to an external power control circuit;
- and
- a redundancy relief circuit, which have a redundancy circuit by which a defective part of the memory is replaced based on the diagnosed result,
- wherein a supply of power to the redundancy relief circuit is controlled independently of a supply of power to the semiconductor integrated circuit by the external power control circuit operating based on the diagnosed result.
Dependencies are inferred from the claim text.