US 6,967,611 B2Granted

Optimized reference voltage generation using switched capacitor scaling for data converters

AssigneeFreescale Semiconductor, Inc.

InventorsAhmad H. Atriss, Steven P. Allen, Douglas A. Garrity

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Abstract

An algorithmic or cyclic data converter uses an RSD stage having a switched capacitor network for efficiently scaling at least one externally supplied reference voltage. A reference voltage is scaled by using capacitor ratios that also function to provide an output voltage used as a residue output of the RSD A/D converter. The residue is used to generate a bit value corresponding to the magnitude of the residue. Two RSD stages cycle back and forth generating a logic value each half clock cycle until the desired bit resolution is achieved. In one form, the RSD stage scales the externally supplied reference voltage only by factors of less than one. In another form, the RSD stage scales the reference voltage by any scaling factor. A reference voltage scaling circuit separate from the RSD stage is avoided.

Claims41

Dependent claims

An analog-to-digital converter (ADC) comprising:

an amplifier comprising an input and an output;
and
a switched capacitor network coupled to the input of the amplifier and being coupled to receive an analog input signal and a plurality of reference input signals input to the ADC comprising at least a first reference input signal and a second reference input signal, the switched capacitor network comprising a plurality of capacitors and switches, each of the plurality of capacitors being coupled to receive at least one of the analog input signal or one of the plurality of reference input signals, wherein the amplifier and switched capacitor network are configured to scale at least one of the plurality of reference input signals by a predetermined scale factor, the predetermined scale factor being determined at least in part by capacitance values of the switched capacitor network, the amplifier and switched capacitor network being further configured to provide an output signal comprising a predetermined gain of the analog input signal adjusted by the predetermined scale factor of the at least one of the plurality of reference input signals, the switched capacitor network comprising a first capacitor controllably coupled to receive the analog input signal, a second capacitor controllably coupled to alternately receive the analog input signal or the first reference input signal, and a third capacitor controllably coupled to alternately receive the analog input signal and the second reference input signal, the third capacitor being further controllably coupled to the first reference input signal and a third reference input signal, and wherein:
the third capacitor is coupled to the analog input signal during a first clock phase;
the third capacitor is coupled to the second reference input signal during a second clock phase when the analog input signal is within a first signal range;
the third capacitor is coupled to the first reference input signal during a second clock phase when the analog input signal is within a second signal range;
and
the third capacitor is coupled to the third reference input signal during the second clock phase when the analog input signal is within a third signal range.

5 more elements

In an analog-to-digital converter (ADC), a processing and scaling circuit comprising:

an amplifier comprising an input and an output, the amplifier having operational range within a power supply range;
and
a switched capacitor circuit coupled to the input of the amplifier and the output of the amplifier, the switched capacitor circuit comprising:
an analog signal input node for receiving an analog signal;
a reference input node for receiving a reference signal capable of having a value outside the operational range of the amplifier;
a plurality of capacitance elements, each of the plurality of capacitance elements being controllably coupled to the analog signal input node or the reference input node, or to both the analog signal input and the reference input node, and being controllably coupled to the input of the amplifier;
wherein,
the amplifier and switched capacitor circuit, responsive to receiving the analog signal and the reference signal, scale the reference signal by a predetermined scale factor to provide a scaled reference signal within the operational range of the amplifier, and process the analog signal to provide an output signal having a predetermined gain of the analog signal adjusted by the predetermined scale factor of the reference signal, the switched capacitor circuit further comprising:
first, second and third capacitors, each having first and second terminals;
a first switch coupled between the first terminal of the first capacitor and the analog signal input node;
a second switch coupled between the first terminal of the second capacitor and the analog signal input node;
a third switch coupled between the first terminal of the second capacitor and a first power supply signal terminal;
and
a fourth switch coupled between the first terminal of the third capacitor and the reference input node;
a fifth switch coupled between the input of the amplifier and at least one of the second terminals of the first, second and third capacitors;
and
a sixth switch coupled between the first power supply signal terminal and at least one of the second terminals of the first, second and third capacitors.

14 more elements

Dependencies are inferred from the claim text.