Cascaded charge pump power supply with different gate oxide thickness transistors

A charge pump power supply for use in a DRAM comprising a charge pump cascade having a plurality of pump stages coupled in series with each pump stage having a FET configured as a diode and a FET configured as a capacitor;

• the FETs of a first of the pump stages having a first oxide thickness and the FETs of a last of the pump stages having a second oxide thickness, the second oxide thickness being greater than the first oxide thickness;
• the first pump stage coupled to a power supply voltage;
• a (2n)th pump stage of the pump cascade is coupled to receive a first non-overlapping clock signal and (2n+1)th pump stage of the pump cascade is coupled to receive a second non-overlapping clock signal, n being an integer greater than or equal to zero;
• and
• a non-overlapping clock signal generator for supplying the first and second non-overlapping clock signals, comprising a system clock input node:
• a clock input stage;
• a latch coupled to the clock input stage having intermediate latch outputs and complementary latch outputs;
• clock output driving stages coupled to the complementary latch outputs and having non-overlapping clock signal outputs;
• and an equalization stage coupled between the clock output driving stages and receiving as inputs the intermediate latch outputs.

A method for providing a charge pump power supply for a DRAM comprising steps of:

• coupling first and second pump cascades in parallel to an output node, each pump cascades having a plurality of pump stages coupled in series;
• providing each pump stage with a FET configured as a diode and a FET configured as a capacitor, the FETs of a first pump stage of each pump cascade having a first oxide thickness and the FETs of a last pump stage of each pump cascade having a second oxide thickness, the second oxide thickness being greater than the first oxide thickness;
• coupling each 2(n)th pump stage of the first pump cascade and each 2(n+1)th pump stage of the second pump cascade to a first non-overlapping clock signal and each 2(n+1)th pump stage of the first pump cascade and each 2(n)th pump stage of the second pump cascade to a second non-overlapping clock signal;
• and
• providing a non-overlapping clock signal generator for supplying the first and second non-overlapping clock signals by coupling a system clock input node to a clock input stage, coupling a latch having intermediate latch outputs and complementary latch outputs to the clock input stage:
• coupling an equalization stage to the intermediate latch outputs and between clock output driving stages:
• and coupling the clock output driving stages to the complementary latch outputs to generate the non-overlapping clock signals.