Non-uniform cache apparatus, systems, and methods
AssigneeBoard of Regents, The University of Texas Systems
InventorsDoug Burger, Stephen W. Keckler, Changkyu Kim
Life of this patent
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Abstract
An apparatus or system may comprises cache control circuitry coupled to a processor, and a plurality of independently accessible memory banks (228) coupled to the cache control circuitry. Some of the banks may have non-uniform latencies, organized into two or more spread bank sets (246). A method may include accessing data in the banks, wherein selected banks are closer to the cache control circuitry and/or processor than others, and migrating a first datum (445) to a closer bank from a further bank upon determining that the first datum is accessed more frequently than a second datum, which may be migrated to the further bank (451).
Claims53
An apparatus, comprising:
- cache control circuitry;
- and
- a plurality of independently accessible memory banks organized as spread bank sets and coupled to the cache control circuitry, wherein at least four of the plurality of independently accessible memory banks have non-uniform latencies.
A processor, comprising:
- an arithmetic functional unit;
- cache control circuitry coupled to the arithmetic logic unit;
- and
- a plurality of independently accessible memory banks coupled to the cache control circuitry, wherein at least two of the plurality of independently accessible memory banks have non-uniform latencies, and wherein the plurality of independently accessible memory banks are organized into at least two spread bank sets.
A system, comprising:
- a processor including cache control circuitry and a plurality of independently accessible memory banks coupled to the cache control circuitry, wherein at least two of the plurality of independently accessible memory banks have non-uniform latencies, and wherein the plurality of independently accessible memory banks are organized into at least two spread bank sets;
- a bus operatively coupled to the processor;
- and
- a random access memory operatively coupled to the bus.
A method, comprising:
- accessing a first datum and a second datum in a plurality of independently accessible memory banks operatively coupled to a processor, wherein at least two of the plurality of independently accessible memory banks have non-uniform latencies, wherein the plurality of independently accessible memory banks are organized into at least two spread bank sets, and wherein a selected one of the plurality of independently accessible memory banks is closer to the processor than a selected other one of the plurality of independently accessible memory banks;
- and
- migrating the first datum to the selected one of the plurality of independently accessible memory banks from the selected other one of the plurality of independently accessible memory banks upon determining that a selected criterion has been met.
A method, comprising:
- accessing a first datum and a second datum in a plurality of independently accessible memory banks operatively coupled to a processor, wherein at least two of the plurality of independently accessible memory banks have non-uniform latencies, wherein the plurality of independently accessible memory banks are organized into a plurality of spread bank sets, and wherein selected ones of the plurality of independently accessible memory banks are closer to the processor than selected other ones of the plurality of independently accessible memory banks;
- and
- migrating the first datum progressively closer to the processor through preselected ones of the plurality of independently accessible memory banks from at least one of the selected other ones of the plurality of independently accessible memory banks to at least one of the selected ones of the plurality of independently accessible memory banks upon determining that the first datum is accessed more frequently than the second datum.
Dependencies are inferred from the claim text.