US 6,965,407 B2 · Image sensor ADC and CDS per column

Abstract

A solid state imager includes an arrangement for converting analog pixel values to digital form on an arrayed per-column basis. An N-bit counter supplies an N-bit DAC to produce an analog ramp output providing a ramp signal with a level that varies corresponding to the contents of the counter. Latches or equivalent digital storage elements are each associated with a respective column. A counter bus connects the counter to latch inputs of said latches, and comparators associated the columns gate the latches when the analog ramp equals the pixel value for that column. The contents of the latch elements are transferred sequentially to a video output bus to produce the digital video signal. There can be additionally black-level readout latch elements, for storing a digital value that corresponds to the dark or black video level, and a subtraction element subtracts the black level value from the pixel value to reduce fixed pattern noise. An additional array of buffer latches can be employed.

Claims10

Dependent claims

Arrangement for converting analog pixel values from an array of pixels to a digital video signal, said array comprising a plurality of columns and at least one row, each column having at one pixel therein, and each column providing a respective pixel value;

the arrangement comprising
an N-bit counter;
an N-bit DAC connected to said counter and having a ramp output providing a signal corresponding to a count existing on said counter;
a plurality of digital storage elements each associated with a respective one of said columns;
a counter bus connecting an output of said counter to inputs of said digital storage elements;
a plurality of comparators each associated with a respective one of said columns, and having one input connected to receive the respective column pixel value, another input connected to the ramp output of said N-bit counter, and a comparator output connected to a gating terminal of the respective digital storage element;
a video readout bus;
and
means selectively transferring contents of said digital storage elements to said video output bus to produce said digital video signal.

6 more elements

the arrangement comprising an N-bit counter;
an N-bit DAC connected to said counter and having a ramp output providing a signal corresponding to a count existing on said counter;
a plurality of digital storage elements each associated with a respective one of said columns;
a counter bus connecting an output of said counter to inputs of said digital storage elements;
a plurality of comparators each associated with a respective one of said columns;
wherein each comparator is made up of a plurality of differential-input amplifiers, each of the differential amplifiers having a plurality of first input transistors, one of the first input transistors being located at each of the pixels within the periphery, and a second input transistor being located outside the periphery of the array and coupled to the first input transistors and to an output configuration circuit, and having one input connected to receive the respective column pixel value, another input connected to the ramp output of said N-bit DAC, and a comparator output connected to a gating terminal of the respective digital storage element;
a video readout bus;
and means selectively transferring contents of said digital storage elements to said video output bus to produce said digital video signal.

5 more elements

Dependencies are inferred from the claim text.

Image sensor ADC and CDS per column

Life of this patent

Image sensor ADC and CDS per column

Life of this patent

Abstract

Claims10