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US 6,965,267 B2Granted
Bipolar differential input stage with input bias current cancellation circuit
AssigneeAnalog Devices, Inc.
InventorsEmmanuel Delorme, Paul Henneuse
Life of this patent
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Abstract
A bipolar differential input stage with an input bias current cancellation circuit comprises an input pair and a bipolar tracking transistor. The input stage is arranged such that the collector currents in the input pair and tracking transistor, and the collector-emitter voltages of the input pair and tracking transistor, are substantially equal. A lateral PNP transistor's first collector provides the tracking transistor base current required to achieve the substantially equal collector current, and second and third collectors provide copies of the tracking transistor base current as bias current cancellation currents to the bases of the input pair, thereby reducing the input stages' input bias currents.
Claims20
A bipolar differential input stage which includes an input bias current cancellation circuit, comprising:
- first and second bipolar input transistors having their bases connected to first and second input terminals, respectively, and their emitters connected together at a common emitter node;
- a first current source connected to said common emitter node and arranged to provide a first bias current Ibias1 to said first and second input transistors;
- a bipolar tracking transistor;
- a second current source which provides a second bias current Ibias2 to said tracking transistor;
- said input stage arranged such that the collector currents in and the collector-emitter voltages of said first and second input transistors and said tracking transistor are substantially equal when the voltages at said first and second input terminals are equal;
- and
- a base current copy circuit arranged to provide a base current Itrk to said tracking transistor required to achieve said substantially equal collector current in said tracking transistor, said copy circuit further arranged to provide first and second bias current cancellation currents Icncl1, Icncl2 to the bases of said first and second input transistors, respectively, such that Icncl1≈Icncl2≈Itrk, thereby reducing the input stages' input bias currents.
4 more elements
A bipolar differential input stage which includes an input bias current-cancellation circuit, comprising:
- first and second bipolar input transistors (Q1, Q2) having their bases connected to first and second input terminals, respectively, and their emitters connected together at a common emitter node, said first and second transistors biased to conduct respective output currents in response to a differential input signal applied to said first and second input terminals;
- first and second bipolar cascode transistors (Q4, Q5) connected in series between said a first supply voltage and said first and second input transistors, respectively, such that said first and second cascode transistors conduct said first and second output currents, the bases of said first and second cascode transistors connected together at a second node;
- a bipolar tracking transistor (Q3) having its emitter connected to said common emitter node;
- a first current source connected to said common emitter node and arranged to provide a first bias current Ibias1 at said common emitter node;
- a third cascode transistor (Q6) having its base connected to said second node and its collector-emitter circuit connected in series between a second current source and said tracking transistor, said second current source arranged such that said third cascode transistor and said tracking transistor conduct a current given by Ibias1/3, such that the collector currents in and the collector-emitter voltages across said first and second input transistors and said tracking transistor are substantially equal when the voltages at said first and second input terminals are equal;
- and
- a base current copy circuit arranged to provide a base current Itrk to said tracking transistor such that it conducts Ibias1/3, said copy circuit further arranged to provide first and second bias current cancellation currents Icncl1, Icncl2 to the bases of said first and second input transistors, respectively, such that Icncl1≈Icncl2≈Itrk, thereby reducing the input stages' input bias currents.
4 more elements
A bipolar differential input stage which includes an input bias current cancellation circuit, comprising:
- first and second bipolar input transistors (Q1, Q2) having their bases connected to first and second input terminals, respectively, and their emitters connected together at a common emitter node, said first and second transistors biased to conduct respective output currents in response to a differential input signal applied to said first and second input terminals;
- first and second bipolar cascode transistors (Q4, Q5) connected in series between said a first supply voltage and said first and second input transistors, respectively, such that said first and second cascode transistors conduct said first and second output currents, the bases of said first and second cascode transistors connected together at a second node;
- a bipolar tracking transistor (Q3) having its emitter connected to said common emitter node;
- a first current source comprising a first current source transistor (Q10) having its collector connected to said common emitter node, its emitter coupled to a second supply voltage, and its base connected to a bias voltage VB, said first current source arranged to provide a first bias current Ibias1 at said common emitter node;
- a second current source comprising a second current source transistor (Q11) having its emitter coupled to said second supply voltage and its base connected to VB, said first and second current sources arranged such that said second current source transistor conducts Ibias1/3;
- a current mirror (Q13/Q14) connected to mirror the current conducted by said second current source transistor to a third node;
- a third cascode transistor (Q6) having its base connected to said second node and its collector-emitter circuit connected in series between said third node and said tracking transistor such that said third cascode transistor and said tracking transistor conduct a current given by Ibias1/3, such that the collector currents in and the collector-emitter voltages across said first and second input transistors and said tracking transistor are substantially equal when the voltages at said first and second input terminals are equal;
- and
- a lateral PNP transistor (Q7) having first, second and third collectors, said lateral PNP transistor having its first collector connected to the base of said tracking transistor and providing Itrk, and its second and third collectors connected to the bases of said first and second input transistors and conducting Icncl1 and Icncl2 to the bases of said first and second input transistors, respectively, said lateral PNP transistor biased such that its emitter-base junction is forward-biased and its base-collector junction is reverse-biased such that said lateral PNP transistor operates in its linear region and Icncl1≈Icncl2≈Itrk, thereby reducing the input stages' input bias currents.
6 more elements
Dependencies are inferred from the claim text.