Reconfigurable digital filter having multiple filtering modes

A hardware-reconfigurable digital filter having multiple filtering modes, comprising:

• logic circuitry adapted to process and mirror data corresponding to filter inputs about a data point corresponding to selected target node in a video image segment, the logic circuitry including registers arrayed in an X-by-Y logical array of registers, wherein Y is greater than X and X is at least 2;
• a computational circuit adapted to perform computations responsive to the logic circuitry and including at least Y multiplication logic circuits and at least Y addition logic circuit;
• and
• mode selection circuitry adapted to direct the digital filter into a mode for performing polyphase transposed filtering by configuring the logic circuitry and the computational circuitry for processing data using the registers in a in a linear configuration which at least two rows of the logical array of registers are coupled together to form a single linear shift register and to direct the digital filter into another filtering mode by configuring the logic circuitry and the computational circuitry for processing data using the registers in a nonlinear configuration different than said linear configuration.

A hardware-reconfigurable digital filter having multiple filtering modes, comprising:

• logic means for processing data corresponding to input data, the logic means including logically arrayed in an X-by-Y logical array of registers for supporting at least one first filtering mode using the registers arranged in a linear configuration which at least two rows of the logical array of registers are coupled together to form a single linear shift register and for supporting at least one second filtering mode using the registers arranged in a nonlinear configuration different than said linear configuration, wherein each of X and Y is at least 2;
• selection means adapted to switch the digital filter between different ones of the multiple filtering modes;
• and
• computational means adapted to perform computations responsive to the logic means and including at least Y multiplication logic circuits and at least Y addition logic circuits.

A hardware-reconfigurable digital filter having multiple filtering modes, comprising:

• logic means for processing and mirroring data corresponding to filter inputs about a data point corresponding to selected target node in a video image segment, the logic circuitry including registers logically arranged in an X-by-Y logical array of registers for supporting at least one first filtering mode using the registers arranged in a linear configuration which at least two rows of the logical array of registers are coupled together to form a single linear shift register and for supporting at least one second filtering mode using the registers arranged in a nonlinear configuration different than said linear configuration, wherein Y is greater than X and X is at least 2;
• means for switching the digital filter between a polyphase transposed filtering mode and at least one other mode of the multiple filtering modes;
• and
• means for performing computations responsive to the logic means and including at least Y multiplication logic circuits and at least Y addition logic circuits, each of the multiplication and addition logic circuits having reconfiguration means responsive to the switching means.

A hardware-reconfigurable digital filter having multiple filtering modes, comprising:

• logic circuitry adapted to process data corresponding to input data, the logic circuitry including a 2-by-6 logical array of registers for supporting a 12-tap FIR filtering mode using the registers arranged in a linear configuration which at least two rows of the logical array of registers are coupled together to form a single linear shift register and, using the registers arranged in a nonlinear configuration different than said linear configuration, for supporting an 11-tap FIR filtering mode in which two of the registers at an end of the array are paired, a polyphase direct filtering mode in which each of six pairs of the registers is used to combine a single input to the pair, and polyphase transposed filtering mode in which six pairs of the registers are used to provide a wide bitwidth corresponding to a high-precision number;
• computational circuitry adapted to perform computations responsive to the logic circuitry and including a multiplication logic circuit and an addition logic circuit, separately arranged, for receiving and processing data from each of the six pairs of registers;
• and
• mode selection circuitry adapted to switch the digital filter between the multiple filtering modes.