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US 6,963,244 B1Granted
Common mode linearized input stage and amplifier topology
AssigneeAnalog Devices, Inc.
InventorNathan R. Carter
Life of this patent
Estimating the term…
Abstract
A common mode linearized input stage comprises NPN and PNP differential pairs biased with respective tail currents at respective common emitter nodes, with each pair connected to receive a differential input signal. A tail current modulation circuit generates complementary output currents as a function of the voltage difference between the common emitter nodes, and first and second tail current sources generate the tail currents as a function of the complementary output currents. The tail current modulation circuit and the first and second tail current sources are arranged such that the magnitudes of the tail currents increase with an increasing differential input signal.
Claims28
A common mode linearized input stage, comprising:
- a differential input terminal Vin+;
- a differential input terminal Vin−, said differential input terminals connected to receive a differential input signal;
- first and second NPN transistors arranged as a differential transistor pair, the bases of said first and second NPN transistors connected to Vin+and Vin−, respectively, the emitters of said first and second NPN transistors connected together at a first node, and the collectors of said first and second NPN transistors conducting respective currents ID1+and ID1−in response to said differential input signal;
- first and second PNP transistors arranged as a differential transistor pair, the bases of said first and second PNP transistors connected to Vin−and Vin+, respectively, the emitters of said first and second PNP transistors connected together at a second node, and the collectors of said first and second PNP transistors conducting respective currents ID2+and ID2−in response to said differential input signal;
- a first tail current source connected to said first node to provide a first tail current Itail1 to said NPN differential transistor pair;
- a second tail current source connected to said second node to provide a second tail current Itail2 to said PNP differential transistor pair;
- and
- a tail current modulation circuit which generates complementary output currents Iin1, Iin2 as a function of the difference between the voltages at said first and second nodes;
- said first tail current source arranged to generate said first tail current Itail1 as a function of Iin1, and said second tail current source arranged to generate said second tail current Itail2 as a function of Iin2, said tail current modulation circuit and said first and second tail current sources arranged such that the magnitudes of tail currents Itail1 and Itail2 increase with an increasing differential input signal.
6 more elements
A common mode linearized input stage, comprising:
- a differential input terminal Vin+;
- a differential input terminal Vin−, said differential input terminals connected to receive a differential input signal;
- first and second NPN transistors arranged as a differential transistor pair, the bases of said first and second NPN transistors connected to Vin+and Vin−, respectively, the emitters of said first and second NPN transistors connected together at a first node, and the collectors of said first and second NPN transistors conducting respective currents ID1+and ID1−in response to said differential input signal;
- first and second PNP transistors arranged as a differential transistor pair, the bases of said first and second PNP transistors connected to Vin−and Vin+, respectively, the emitters of said first and second PNP transistors connected together at a second node, and the collectors of said first and second PNP transistors conducting respective currents ID2+and ID2−in response to said differential input signal;
- a first tail current source connected to said first node to provide a first tail current Itail1 to said NPN differential transistor pair;
- a second tail current source connected to said second node to provide a second tail current Itail2 to said PNP differential transistor pair;
- a PNP diversion transistor having its base connected to said first node, its collector coupled to said first tail current source, and its emitter connected to a third node;
- and
- a NPN diversion transistor having its base connected to said second node, its collector coupled to said second tail current source, and its emitter connected to said third node, such that said PNP and NPN diversion transistors conduct complementary output currents Iin1 and Iin2, respectively, as a function of the difference between the voltages at said first and second nodes;
- said first tail current source arranged to generate Itail1 as a function of Iin1 and said second tail current source arranged to generate Itail2 as a function of Iin2, such that the magnitudes of Itail1 and Itail2 increase with an increasing differential input signal.
7 more elements
A common mode linearized input stage, comprising:
- a differential input terminal Vin+;
- a differential input terminal Vin−, said differential input terminals connected to receive a differential input signal;
- first and second NPN transistors arranged as a differential transistor pair, the bases of said first and second NPN transistors connected to Vin+and Vin−, respectively, the emitters of said first and second NPN transistors connected together at a first node, and the collectors of said first and second NPN transistors conducting respective currents ID1+and ID1−in response to said differential input signal;
- first and second PNP transistors arranged as a differential transistor pair, the bases of said first and second PNP transistors connected to Vin−and Vin+, respectively, the emitters of said first and second PNP transistors connected together at a second node, and the collectors of said first and second PNP transistors conducting respective currents ID2+and ID2−in response to said differential input signal,
- said first and second NPN transistors and said first and second PNP transistors each having an emitter size of 1;
- a first tail current source connected to said first node to provide a first tail current Itail1 to said NPN differential transistor pair;
- a second tail current source connected to said second node to provide a second tail current Itail2 to said PNP differential transistor pair;
- a PNP diversion transistor having its base connected to said first node, its collector coupled to said first tail current source, and its emitter connected to a third node;
- and
- a NPN diversion transistor having its base connected to said second node, its collector coupled to said second tail current source, and its emitter connected to said third node, said PNP and NPN diversion transistors each having an emitter size of A,
- such that said PNP and NPN diversion transistors conduct and thereby divert said first and second tail currents from said NPN and PNP differential transistor pairs by a scaling ratio of A when said differential input signal is zero;
- said input stage arranged such that the current ID1+conducted by said first NPN transistor is given by:
- I
- D1
- +
- =
- e
- α
- e
- α
- +
- A
- +
- e
- -
- α
- *
- I
- 1
-
- (
- max
- )
- the current conducted by said second NPN transistor is given by:
- I
- D1
- -
- =
- e
- -
- α
- e
- α
- +
- A
- +
- e
- -
- α
- *
- I
- 1
-
- (
- max
- )
- and the current Idiv conducted by said PNP and NPN diversion transistors is given by:
- I
- div
- =
- A
- e
- α
- +
- A
- +
- e
- -
- α
- where α is given by:
- α
- =
- V
- in
- +
- -
- V
- in
- -
- 2
- *
- V
- t
- ,
- where Vt is the thermal voltage
- kT
- q
- ,
- and the transconductance Gm of the input stage is given by:
- G
- m
- =
- 2
-
- A
- *
- cosh
-
-
- α
- +
- 4
- (
- 2
- *
- cosh
-
-
- α
- +
- A
- )
- 2
- ·
- ⅆ
- α
- ⅆ
- (
- V
- in
- +
- -
- V
- in
- -
- )
- ·
- I
- (
- max
- )
-
-
- assuming
- I
- 1
-
- (
- max
- )
- =
- I
- 2
-
- (
- max
- )
- =
- I
- (
- max
- )
- .
150 more elements
A common mode linearized input stage, comprising:
- first and second supply voltages;
- a differential input terminal Vin+;
- a differential input terminal Vin−, said differential input terminals connected to receive a differential input signal;
- first and second NPN transistors arranged as a differential transistor pair, the bases of said first and second NPN transistors connected to Vin+and Vin−, respectively, the emitters of said first and second NPN transistors connected together at a first node, and the collectors of said first and second NPN transistors conducting respective currents in response to said differential input signal;
- first and second PNP transistors arranged as a differential transistor pair, the bases of said first and second PNP transistors connected to Vin−and Vin+, respectively, the emitters of said first and second PNP transistors connected together at a second node, and the collectors of said first and second PNP transistors coupled to said second supply voltage;
- a first tail current source connected between said first node and said second supply voltage to provide a first tail current Itail1 to said NPN differential transistor pair;
- a second tail current source connected between said first supply voltage and said second node to provide a second tail current Itail2 to said PNP differential transistor pair;
- a PNP diversion transistor having its base connected to said first node, its collector coupled to said first tail current source, and its emitter connected to a third node;
- and
- a NPN diversion transistor having its base connected to said second node, its collector coupled to said first supply voltage, and its emitter connected to said third node,
- such that said PNP and NPN diversion transistors conduct and thereby divert said first tail current from said NPN differential transistor pair when said differential input signal is zero.
8 more elements
An amplifier, comprising:
- an input stage;
- and
- an input stage mirroring structure;
- said input stage comprising:
- a differential input terminal Vin+;
- a differential input terminal Vin−, said differential input terminals connected to receive a differential input signal;
- first and second NPN transistors arranged as a differential transistor pair, the bases of said first and second NPN transistors connected to Vin+and Vin−, respectively, the emitters of said first and second NPN transistors connected together at a first node, and the collectors of said first and second NPN transistors conducting respective currents ID1+and ID1−in response to said differential input signal;
- first and second PNP transistors arranged as a differential transistor pair, the bases of said first and second PNP transistors connected to Vin−and Vin+, respectively, the emitters of said first and second PNP transistors connected together at a second node, and the collectors of said first and second PNP transistors conducting respective currents ID2+and ID2−in response to said differential input signal;
- a first tail current source connected to said first node to provide a first tail current Itail1 to said NPN differential transistor pair;
- a second tail current source connected to said second node to provide a second tail current Itail2 to said PNP differential transistor pair;
- a tail current modulation circuit which generates complementary output currents Iin1, Iin2 as a function of the difference between the voltages at said first and second nodes;
- said first tail current source arranged to generate said first tail current Itail1 as a function of Iin1, and said second tail current source arranged to generate said second tail current Itail2 as a function of Iin2, said tail current modulation circuit and said first and second tail current sources arranged such that the magnitudes of tail currents Itail1 and Itail2 increase with an increasing differential input signal;
- said input stage mirroring structure connected between first and second supply voltages and which receives said currents ID1+, ID1−, ID2+and ID2−and produces an output current in response, said input stage mirroring structure comprising:
- a first current mirror circuit having an input and output, said differential output currents ID1+and ID1−coupled to first current mirror circuit at third and fourth nodes, respectively, said first current mirror circuit arranged such that ID1+and ID1−inject offset current into an otherwise balanced current mirror such that the current at said first current mirror circuit's output varies only when ID1+and ID1−are unequal;
- a second current mirror circuit having an input and output and complementary to said first current mirror circuit, said differential output currents ID2+and ID2−coupled to second current mirror circuit at fifth and sixth nodes, respectively, said second current mirror circuit arranged such that ID2+and ID2−inject offset current into an otherwise balanced current mirror such that the current at said second current mirror circuit's output varies only when ID2+and ID2−are unequal;
- a single floating current source connected between the inputs of said first and second current mirror circuits, the outputs of said first and second current mirror circuits coupled to an output node, the current at said output node being said output current;
- such that noise due to said floating current source is correlated for the two current mirror circuits such that its noise sums to zero at said output node, said input stage connected to said mirroring structure in a balanced fashion such that a change in Itail1 shifts the voltages at said third and fourth nodes by equal amounts and a change in Itail2 shifts the voltages at said fifth and sixth nodes by equal amounts without changing said output current, thereby rejecting common mode noise.
14 more elements
Dependencies are inferred from the claim text.