US 6,962,867 B2Granted

Methods of fabrication of semiconductor dice having back side redistribution layer accessed using through-silicon vias and assemblies thereof

AssigneeMicronTechnology, Inc.

InventorsTimothy L. Jackson, Tim E. Murphy

Life of this patent

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Abstract

An apparatus and method of rerouting redistribution lines from an active surface of a semiconductor substrate to a back surface thereof and assembling and packaging individual and multiple semiconductor dice with such rerouted redistribution lines formed thereon. The semiconductor substrate includes one or more vias having conductive material formed therein and which extend from an active surface to a back surface of the semiconductor substrate. The redistribution lines are patterned on the back surface of the semiconductor substrate, extending from the conductive material in the vias to predetermined locations on the back surface of the semiconductor substrate that correspond with an interconnect pattern of another substrate for interconnection thereto.

Claims28

Dependent claims

A method of making a semiconductor substrate, the method comprising:

providing at least one semiconductor die having an active surface and a back surface, the at least one semiconductor die defining at least one via having a substantially uniform cross section therethrough extending from the active surface to the back surface thereof;
disposing conductive material in the at least one via to substantially extend therethrough from the active surface to the back surface of the at least one semiconductor die wherein the conductive material completely fills the at least one via;
forming at least one electrically conductive redistribution line on the active surface of the at least one semiconductor die in electrical communication with the conductive material of the at least one via and extending to a predetermined location on the active surface of the at least one semiconductor die remote from the location of the at least one via;
and
forming at least one electrically conductive redistribution line on the back surface of the at least one semiconductor die in electrical communication with the conductive material of the at least one via and extending to a predetermined location on the back surface of the at least one semiconductor die remote from the location of the at least one via.

2 more elements

A method of assembling a semiconductor assembly comprising:

providing a substrate having a first surface and a second surface and at least one electrical interconnect on the first surface;
providing a first semiconductor die having an active surface bearing integrated circuitry and a back surface, the first semiconductor die defining at least one via having a substantially uniform cross section extending from the active surface to the back surface with conductive material formed therein, wherein the conductive material completely fills the at least one via, the active surface having at least one redistribution line thereon extending from the conductive material in the at least one via to a predetermined location on the active surface, the back surface having at least one redistribution line thereon extending from the conductive material in the at least one via to a predetermined location on the back surface;
and
attaching the back surface of the first semiconductor die to the first surface of the substrate so that the at least one electrical interconnect on the first surface is electrically connected to the at least one redistribution line at the predetermined location on the back surface of the first semiconductor die.

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 10/732,558Filed 10 Dec 2003 · division
Priority: 31 Jul 2002
Published: US 2004/0021139 A124 Jun 2004
Granted: 8 Nov 2005
Term ends: Not estimatedThe source records don’t support an estimate.

Classification31 codes

H10W 90/00
Package configurations
H10W 20/023
Of interconnections within wafers or substrates: the interconnections being through-semiconductor vias
H10W 20/0245
The interconnections being through-semiconductor vias: comprising use of blind vias during the manufacture
H10W 20/20
Interconnections in chips, wafers or substrates: interconnections within wafers or substrates, e.g. through-silicon vias [TSV]

Family

Application10/209,823Parent of this division · filed 31 Jul 2002
US 2004/0121521 A1Pre-grant publication · published 24 Jun 2004
US 6,800,930 B2Parent of this division
US 2004/0021139 A1Published application
US 6,962,867 B2This patent

From the US filing history. Foreign family members aren’t listed.