# US 6,962,829 B2 · Method of making near chip size integrated circuit package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 6,962,829 B2 - Document ID: US6962829B2 - Status: Granted - Kind: B2 - Application number: 10/150,400 - Filed: 2002-05-17 - Published: 2002-11-14 - Granted: 2005-11-08 - Earliest claimed: 1996-10-31 - Assignees: Amkor Technology, Inc. - Inventors: Thomas P. Glenn; Roy D. Hollaway; Anthony E. Panczak - Web page: https://patentgrep.com/patent/US6962829B2 ## CPC - H10W 74/014: {using batch processing} - H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons - H10W 42/284: {shielding resins} - H10W 74/01: Manufacture or treatment - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 70/656: Fan-in layouts - H10W 72/0198: {batch processes} - H10W 72/5522: {comprising gold [Au]} - H10W 72/5524: {comprising aluminium [Al]} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 72/90: Bond pads, in general - H10W 72/9415: {relative to the surface, e.g. recessed, protruding} - H10W 72/9445: {Top-view layouts, e.g. mirror arrays} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/10: characterised by their shape or disposition - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - Y10T 29/49135: and shaping, e.g., cutting or bending, etc. - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION ## Abstract A plurality of integrated circuit chip (IC chip) packages are fabricated simultaneously from a single insulating substrate having sections. In each section, an IC chip is attached. Bonding pads on the IC chip are electrically connected to first metallizations on a substrate first surface. The first metallizations, IC chip including bonding pads and first substrate surface are then encapsulated. Interconnection balls or pads are formed at substrate bonding locations on a substrate second surface, the interconnection pads or balls being electrically connected to corresponding first metallizations. The substrate and encapsulant are then cut along the periphery of each section to form the plurality of IC chip packages. ## Claims ### Claim 1 A method of forming a plurality of integrated circuit chip packages, said method comprising: providing a substrate having a plurality of sections, each of said sections having first metallizations formed on a first surface of said substrate; coupling an integrated circuit chip to a corresponding one of each of said sections of said substrate; electrically connecting each said integrated circuit chip to said first metallizations on said corresponding one of said sections; encapsulating said integrated circuit chips, said first metallizations and said first surface of said substrate with a layer of an encapsulant, wherein said layer of the encapsulant has an outer surface overlying the integrated circuit chips; placing the outer surface of the layer of the encapsulant on a mounting surface, and immobilizing the encapsulated substrate on said mounting surface; cutting said encapsulated substrate while on said mounting surface along a periphery of each of said sections to form said plurality of integrated circuit chip packages. ### Claim 2 (depends on 1) The method of claim 1, wherein said mounting surface is a tape with an adhesive layer thereon, wherein the adhesive layer immobilizes the encapsulated substrate, and the layer of the encapsulant comprises a first layer of an electrically insulative encapsulant, and a second layer of an electrically conductive encapsulant at said outer surface. ### Claim 3 (depends on 1) The method of claim 1, further comprising electrically testing said packages while said packages are immobilized on said mounting surface. ### Claim 4 (depends on 1) The method of claim 1, wherein each of said sections has second metallizations formed on a second surface of said substrate opposite said first surface and electrically conductive paths extending through said substrate from said first metallizations to said second metallizations. ### Claim 5 (depends on 4) The method of claim 4, further comprising forming interconnection balls on said second surface of said substrate at each of said sections, each of said interconnection balls being in electrical connection with one of said second metallizations. ### Claim 6 (depends on 1) The method of claim 1, wherein the layer of the encapsulant comprises a first layer of an electrically insulative encapsulant, and a second layer of an electrically conductive encapsulant at said outer surface. ### Claim 7 (depends on 1) The method of claim 1, wherein said mounting surface is a tape with an adhesive layer thereon, wherein the adhesive layer contacts the outer surface of the layer of encapsulant and thereby immobilizes the encapsulated substrate. ### Claim 8 A method of forming a plurality of integrated circuit chip packages, said method comprising the steps of: providing a substrate having a first surface and a plurality of sections, each said section having an integrated circuit chip coupled to the first surface of the substrate within the respective section, wherein a layer of an encapsulant covers the first surface of the substrate and the integrated circuit chips, said layer of the encapsulant having an outer surface overlying the integrated circuit chips; placing the outer surface of the layer of the encapsulant on a mounting surface, and immobilizing the encapsulated substrate thereon; cutting said encapsulated substrate along a periphery of each of said sections to form said plurality of integrated circuit chip packages. ### Claim 9 (depends on 8) The method of claim 8, wherein said mounting surface is a tape with an adhesive layer thereon, wherein the adhesive layer immobilizes the encapsulated substrate, and the layer of the encapsulant comprises a first layer of an electrically insulative encapsulant, and a second layer of an electrically conductive encapsulant at said outer surface. ### Claim 10 (depends on 8) The method of claim 8, further comprising electrically testing said packages while said packages are immobilized on said mounting surface. ### Claim 11 (depends on 10) The method of claim 10, further comprising forming interconnection balls on a second surface of said substrate at each of said sections, said interconnection balls being electrically coupled to the integrated circuit chip of the respective section. ### Claim 12 (depends on 8) The method of claim 8, wherein the layer of the encapsulant comprises a first layer of an electrically insulative encapsulant, and a second layer of an electrically conductive encapsulant at said outer surface. ### Claim 13 (depends on 8) The method of claim 8, wherein said mounting surface is a tape with an adhesive layer thereon, wherein the adhesive layer contacts the outer surface of the layer of encapsulant and thereby immobilizes the encapsulated substrate. ### Claim 14 A method of forming a plurality of integrated circuit chip packages, said method comprising the steps of: providing a substrate having a plurality of sections, each said section having an integrated circuit chip coupled to a first surface of the substrate within the section, wherein a layer of an encapsulant covers the first surface of the substrate and the integrated circuit chips, said layer of the encapsulant having an outer surface overlying the integrated circuit chips; placing the outer surface of the layer of the encapsulant on a mounting surface, and immobilizing the encapsulated substrate thereon; and cutting said encapsulated substrate from the substrate through the layer of the encapsulant along a periphery of each of said sections while immobilized on said mounting surface to form said plurality of integrated circuit chip packages. ### Claim 15 (depends on 14) The method of claim 14, wherein said mounting surface is a tape with an adhesive layer thereon, wherein the adhesive layer immobilizes the encapsulated substrate, and the layer of the encapsulant comprises a first layer of an electrically insulative encapsulant, and a second layer of an electrically conductive encapsulant at said outer surface. ### Claim 16 (depends on 15) The method of claim 15, further comprising electrically testing said packages while said packages are immobilized on said mounting surface. ### Claim 17 (depends on 16) The method of claim 16, further comprising forming interconnection balls on a second surface of said substrate at each of said sections, each of said interconnection balls being in electrical connection with the integrated circuit chip of the respective section. ### Claim 18 (depends on 14) The method of claim 14, wherein the layer of the encapsulant comprises a first layer of an electrically insulative encapsulant, and a second layer of an electrically conductive encapsulant at said outer surface. ### Claim 19 (depends on 14) The method of claim 14, wherein said mounting surface is a tape with an adhesive layer thereon, wherein the adhesive layer contacts the outer surface of the layer of encapsulant and thereby immobilizes the encapsulated substrate.