Back to results
US 6,959,435 B2Granted
Compiler-directed speculative approach to resolve performance-degrading long latency events in an application
AssigneeIntel Corporation
InventorsDz-Ching Ju, Youfeng Wu
Life of this patent
Estimating the term…
Abstract
A compiler-directed speculative approach to resolve performance-degrading long latency events in an application is described. One or more performance-degrading instructions are identified from multiple instructions to be executed in a program. A set of instructions prefetching the performance-degrading instruction is defined within the program. Finally, at least one speculative bit of each instruction of the identified set of instructions is marked to indicate a predetermined execution of the instruction.
Claims23
A method comprising:
- identifying at least one performance-degrading instruction from a plurality of instructions to be executed in a program;
- defining a set of instructions within said program to prefetch said at least one performance-degrading instruction;
- marking at least one speculative bit of each instruction of said set of instructions to indicate a predetermined execution of said each instruction;
- and
- inserting a launch point to launch said predetermined execution, said inserting further comprising:
- determining a first instruction of said set of instructions;
- determining whether variables of said set of instructions are ready for execution;
- and
- determining whether a latency value from said launch point to said performance-degrading instruction is greater than a total latency value of said set of instructions including a miss latency of said performance-degrading instruction.
6 more elements
A system comprising:
- means for identifying at least one performance-degrading instruction from a plurality of instructions to be executed in a program;
- means for defining a set of instructions within said program to prefetch said at least one performance-degrading instruction;
- means for marking at least one speculative bit of each instruction of said set of instructions to indicate a predetermined execution of said each instruction;
- and
- means for inserting a launch point to launch said predetermined execution, said means for inserting further comprising:
- means for determining a first instruction of said set of instructions;
- means for determining whether variables of said set of instructions are ready for execution;
- and
- means for determining whether a latency value from said launch point to said performance-degrading instruction is greater than a total latency value of said set at instructions including a miss latency of said performance-degrading instruction.
6 more elements
A computer readable medium containing executable instructions, which, when executed in a processing system, cause said processing system to perform a method comprising:
- identifying at least one performance-degrading instruction from a plurality of instructions to be executed in a program;
- defining a set of instructions within said program to prefetch said at least one performance-degrading instruction;
- marking at least one speculative bit of each instruction of said set of instructions to indicate a predetermined execution of said each instruction;
- and
- inserting a launch point to launch said predetermined execution, said inserting further comprising:
- determining a first instruction of said set of instructions;
- determining whether variables of said set of instructions are ready for execution;
- and
- determining whether a latency value from said launch point to said performance-degrading instruction is greater than a total latency value of said set of instructions including a miss latency of said performance-degrading instruction.
6 more elements
A system comprising:
- a memory to store a plurality of instructions to be executed in a program;
- and
- a processor coupled to said memory to:
- identify at least one performance-degrading instruction from said plurality of instructions;
- define a set of instructions within said program to prefetch said at least one performance-degrading instruction;
- mark at least one speculative bit of each instruction of said set of instructions to indicate a predetermined execution of said each instruction;
- and
- insert a launch point to launch said predetermined execution, wherein to insert a launch point further comprises said processor to:
- determine a first instruction of said set of instructions;
- determine whether variables of said set of instructions are ready for execution;
- and
- determine whether a latency value from said launch point to said at least one performance-degrading instruction is greater than a total latency value of said set of instructions including a miss latency of said performance-degrading instruction.
9 more elements
Dependencies are inferred from the claim text.