Designing and testing the interconnection of addressable devices of integrated circuits

An article of manufacture, comprising a data storage medium tangibly embodying a program of machine readable instructions executable by an electronic processing apparatus to perform method steps for operating an electronic processing apparatus, said method steps comprising the steps of:

• (a) reading a plurality of input files relating to a plurality of addressable registers and addressable memories to be designed into a semiconductor product, the input files comprising a functional description of a desired semiconductor product;
• a configuration for an internal and/or external bus used with the semiconductor product;
• address parameters for the addressable registers and/or addressable memories;
• (b) accessing a design database comprising an application set upon which the desired semiconductor product will be designed, and accessing a number of tests for any new generated logic to be included for the design of the desired semiconductor product;
• (c) generating a plurality of output files relating to interconnecting the addressable registers and/or addressable memories with the bus;
• and
• (d) updating the design database with the output files.

A register address generation tool, comprising:

• (a) means to receive a functional description and address parameters of a plurality of addressable registers and/or addressable memories to be created on a desired semiconductor product;
• (b) means to receive a configuration of an internal and/or external bus to be connected to at least a portion of the plurality of addressable registers and/or the plurality of addressable memories;
• (c) means to receive input from and provide output to a design database having at least an application set describing a partially manufactured integrated circuit upon which the desired semiconductor product will be built;
• (d) means to generate interconnect register transfer logic to connect the bus to the portion of addressable registers and/or addressable memories;
• and
• (e) means to update the design database with the interconnect register transfer logic.