IC with serial scan path, protocol memory, and event circuit

An integrated circuit comprising:

• A. a substrate;
• B. operating circuits formed on the substrate, the operating circuits including an operating bus of plural leads for carrying normal operating signals;
• C. a serial data input lead formed on the substrate, a serial data output lead formed on the substrate, and a plurality of serial scan paths, each formed of scan registers, formed on the substrate and coupled between the serial data input lead and the serial data output lead, the serial scan paths for carrying serial data signals, including command signals, an expected data pattern signals, and a protocol selection signal, on the substrate,
• i. one of the plurality of serial scan paths including a data register having plural data storage locations, a serial input coupled between the serial data input lead and the data storage locations for carrying serial data signals to the data storage locations, a serial output coupled between the serial data output lead and the data storage locations for carrying signals out of the data storage locations, data inputs coupled between the data storage locations and the operating bus for carrying the normal operating signals to the data storage locations, and a control input, and
• ii. another of the plurality of serial scan paths including a command register, the command register having plural command storage locations for storing command signals, a control input, a serial input coupled between the serial data input lead and the command storage locations for carrying the command signals to the storage locations, and a serial output coupled to the serial data output lead;
• D. an expected data memory formed on the substrate, the expected data memory having plural expected data pattern storage locations for storing an expected data pattern signals and having at least one input coupled between one of the serial scan paths and the expected data storage locations for receiving the expected data pattern signals from the serial scan path;
• E. a comparator formed on the substrate, the comparator having first inputs coupled to the operating bus and second inputs coupled to the expected data memory for comparing at least some of the normal operating signals to corresponding ones of the expected data pattern signals, the comparator having a compare output lead;
• F. a mode select input lead formed on the substrate, the mode select input lead for carrying a mode select signal;
• G. a serial data clock input lead formed on the substrate, the serial data clock input lead for carrying a serial data clock signal;
• H. an access port formed on the substrate, the access port including control circuitry and having a plurality of control outputs, at least one first control output coupled to the control input of the command register, at least one second control output coupled to the control input of the data register, a first input coupled to the mode select input lead and a second input coupled to the serial data clock input lead, the control circuitry being operable selectively to control shifting of the serial data signals between the serial data input lead and the serial data output lead, and into and out of the command register, and into and out of the data register responsive to the mode select signal and the serial data clock signal;
• J. a protocol selection memory having at least one storage location for storing a protocol selection signal, and an input coupled to one of the serial scan paths, the protocol selection memory storage location for receiving the protocol selection signal from the serial scan path;
• and
• K. an event control circuit including a protocol input coupled to the protocol selection memory, an event input lead coupled to the compare output lead, and an event output lead.