Universal asynchronous boundary module
AssigneeHewlett-Packard Development Company, L.P.
InventorsParas A. Shah, Prashantha Kalluraya
Life of this patent
Estimating the term…
Abstract
An application specific integrated circuit (ASIC) employs various logic blocks. The blocks may include logic circuits that operate at different clock rates. Consequently, an interface logic block may be needed to efficiently transfer signals from one frequency clock domain to another. One such interface, known as a universal asynchronous boundary module (UABM) is situated between the two domains allowing communication between the logic circuits.
Claims21
A computer system, comprising:
- a first logic circuit;
- a second logic circuit;
- and
- an interface coupling the first logic circuit to the second logic circuit, wherein the interface includes:
- an input logic block that receives an incoming data stream and a first clock from the first logic circuit, the input logic block provides an intermediate signal, wherein if the incoming data stream includes a first asserted signal, the intermediate signal inverts its logic state, wherein the input logic block includes;
- a multiplexor, the multiplexor receives the incoming data stream;
- and
- a first register coupled to the multiplexor;
- the first register is clocked by the first clock;
- wherein the multiplexor provides the first register the inverted version of the output of the first register when the incoming data stream includes the first asserted signal, the first register provides the intermediate signal;
- and
- an output logic block coupled to the input logic block, the output logic block receives the intermediate signal and a second clock, wherein the output logic block provides to the second logic circuit an output signal, the output signal is a second asserted signal for one clock period of the second clock, when the output logic block detects a logic state change in the intermediate signal.
An interface coupling a first logic circuit to a second logic circuit, comprising,
- an input logic block that receives an incoming data stream and a first clock from the first logic circuit, the input logic block provides an intermediate signal, wherein if the incoming data stream includes a first asserted signal, the intermediate signal inverts its logic state, wherein the input logic block includes;
- a multiplexor, the multiplexor receives the incoming data stream;
- and
- a first register coupled to the multiplexor;
- the first register is clocked by the first clock;
- wherein the multiplexor provides the first register the inverted version of the output of the first register when the incoming data stream includes the first asserted signal, the first register provides the intermediate signal;
- and
- an output logic block coupled to the input logic block, the output logic block receives the intermediate signal and a second clock, wherein the output logic block provides to the second logic circuit an output signal, the output signal is a second asserted signal for one clock period of the second clock, when the output logic block detects a logic state change in the intermediate signal.
A method for coupling a first logic circuit to a second logic circuit, comprising the step of:
- providing an input data stream from a first logic circuit clocked by a first clock to a first register;
- ascertaining a first asserted signal in the input data stream;
- creating an intermediate signal by inverting the output of the first register when the first asserted signal is received;
- comparing the logic states of the intermediate signal at different times, the different times equal to a first time period of a second clock;
- outputting a second asserted signal to a second logic circuit for a period equaled to the second clock when the logic states of the intermediate signal are different during the first time period.
Dependencies are inferred from the claim text.