US 6,959,397 B2 · Programmable skew clock signal generator selecting one of a plurality of delayed reference clock signals in response to a phase accumulator output

Abstract

A programmable skew clock signal generator has a frequency generator circuit (104) consistent with the invention produces an output signal Fφ0 from a reference signal Fref A frequency accumulator (132, 152) is preloaded with a preload value PK1 and receives one reference signal cycle as a clock signal, receives a constant K1 as an input thereto, with the frequency accumulator (132, 152) having a maximum count KMAX and producing an overflow output. A phase accumulator (136, 156) is preloaded with a preload value PC1 and receives one overflow cycle output from the frequency accumulator (132, 152) as a clock signal and receives a phase offset constant C1 as an input thereto. The phase accumulator (136, 156) has a maximum count CMAX and produces a phase accumulator (136, 156) output. A delay line (320) is clocked by the reference signal Fref and produces a plurality of delayed reference clock signals at a plurality of tap outputs. A tap selecting circuit (140, 144; 160, 164) receives the phase accumulator output and selects at least one of the tap outputs in response thereto to produce an output Fφ1 whose phase shift φ1 relative to F0φ is a function of PK1 and PC1.

Drawings

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Drawings

Claims25

Dependent claims

A programmable skew clock signal generator, comprising:

a frequency generator circuit that produces an output signal Fφ0 from a reference signal Fref;
a frequency accumulator, preloaded with a preload value PK1 for a first reference signal cycle and receiving a frequency division constant K1 as an input thereto for subsequent cycles of Fref, the frequency accumulator having a maximum count KMAX and producing an overflow output;
a phase accumulator, receiving the overflow output from the frequency accumulator as a clock signal, preloaded with a preload value PC1 for a first cycle of the overflow output from the frequency accumulator and receiving a phase offset constant C1 as an input thereto during subsequent cycles of the overflow output from the frequency accumulator, the phase accumulator having a maximum count CMAX and producing a phase accumulator output;
a delay line clocked by the reference signal Fref and producing a plurality of delayed reference clock signals at a plurality of tap outputs;
tap selecting means receiving the phase accumulator output and selecting at least one of the tap outputs in response thereto to produce an output Fφ1 whose phase shift φ1 relative to Fφ0 is a function of PK1 and PC1;
and
wherein the output Fφ1 is given by:
x
⁡
(
t
)
=
rect
⁡
(
t
T
p
)
=
{
1
for
⁢
⁢

t

<
T
p
2
0
otherwise
⁢
⁢
F
ϕ
⁢
1
=
∑
n
=
0
∞
⁢
x
⁡
[
t
-
n
⁢
⁢
T
ϕ
⁢
⁢
1
-
ϕ
]
,
where t is a time corresponding to a center of an output pulse, Tp is the width of the output pulse, and Tφ1 is the period of the pulse train, and wherein PK1 and PC1 are respectively given by:
P
K1
=
ϕ
2
⁢
π
·
K
MAX
⁢
⁢
and
⁢
⁢
P
C1
=
[
K
MAX
-
Frac
⁡
(
P
K1
K
)
]
·
C
MAX
.

97 more elements

A programmable skew clock signal generator, comprising:

a frequency generator circuit that produces an output signal Fφ0 from a reference signal Fref;
first and second frequency accumulators, preloaded with a preload values PK1 and PK2 for a first cycle of the reference signal and receiving constants K1 and K2 as inputs thereto for subsequent cycles of the reference signal respectively, and producing first and second overflow outputs, the first and second frequency accumulators having a maximum count KMAX1 and KMAX2;
first and second phase accumulators, preloaded with preload values PC1 and PC2 respectively during an initial output from first and second overflow outputs respectively from the first and second frequency accumulators as clock signals, and receiving first and second phase offset constants C1 and C2 respectively as inputs thereto during subsequent accumulator overflow cycles, and producing first and second phase accumulator outputs, the first and second phase accumulators having a maximum count CMAX2 and CMAX2;
a delay line clocked by the reference input signal and producing a plurality of delayed reference clock signals at a plurality of tap outputs;
and
first and second tap selecting circuits, receiving the first and second phase accumulator outputs respectively, the first and second tap selecting circuits each selecting at least one of the tap outputs in response to the first and second phase accumulator outputs to produce first and second outputs Fφ1 and Fφ2, where phase shift φ1 relative to Fφ0 is a function of PK1 and PC1 and phase shift φ2 relative to Fφ0 a function of PK2 and PC2.

3 more elements

A programmable skew clock signal generator, comprising:

a delay line clocked by a reference signal Fref and producing a plurality of delayed reference clock signals at a plurality of tap outputs, the delay line being locked in a delay locked loop;
a frequency generator circuit that produces an output signal Fφ0 from the reference signal Fref, the frequency generator circuit comprising:
a reference frequency accumulator, preloaded with a preload value PK0 during a first reference signal cycle as a clock signal and receiving a constant K0 as an input during subsequent reference signal cycles, the frequency accumulator having a maximum count KMAX and producing an overflow output,
a reference phase accumulator, preloaded with a preload value PC0 during a first accumulator overflow cycle from the frequency accumulator as a clock signal, and receiving a phase offset constant C0 as an input thereto during subsequent frequency accumulator overflow cycles, the phase accumulator having a maximum count CMAX and producing a phase accumulator output, and
reference tap selecting means receiving the phase accumulator output and selecting at least one of the tap outputs in response thereto to produce an output Fφ0;
first and second frequency accumulators, preloaded with a preload values PK1 and PK2 during a first reference input signal cycle as a clock signal, and subsequently receiving constants K1 and K2 as inputs thereto respectively, and producing first and second overflow outputs, the first and second frequency accumulators having a maximum count KMAX1 and KMAX2;
first and second phase accumulators, preloaded with preload values PC1 and PC2 respectively during an initial cycle of the first and second overflow outputs respectively from the first and second frequency accumulators as clock signals, and subsequently receiving first and second phase offset constants C1 and C2 respectively as inputs thereto, and producing first and second phase accumulator outputs, the first and second phase accumulators having a maximum count CMAX2 and CMAX2;
and
first and second tap selecting circuits, receiving the first and second phase accumulator outputs respectively, the first and second tap selecting circuits each selecting at least one of the tap outputs in response to the first and second phase accumulator outputs to produce first and second outputs Fφ1 and Fφ2, where phase shift φ1 relative to Fφ0 is a function of PK1 and PC1 and phase shift φ2 relative to Fφ0 is a function of PK2 and PC2, wherein,
the output Fφ1 is given by:
x
⁡
(
t
)
=
rect
⁡
(
t
T
p
)
=
{
1
for
⁢
⁢

t

<
T
p
2
0
otherwise
F
ϕ
⁢
⁢
1
=
∑
n
=
0
∞
⁢
⁢
x
⁡
[
t
-
n
⁢
⁢
T
ϕ
⁢
⁢
1
-
ϕ
]
,
where t is a time corresponding to a center of an output pulse, Tp is the width of the output pulse, and Tφ1 is the period of the pulse train, and wherein PK1 and PC1 are respectively given by
P
K1
=
ϕ
1
2
⁢
π
·
K
MAX
⁢
⁢
and
⁢
⁢
P
C1
=
[
K
MAX
-
Frac
⁡
(
P
K1
K
)
]
⁢
C
MAX
;
and
wherein the output Fφ2 is given by:
x
⁡
(
t
)
=
rect
⁡
(
t
T
p
)
=
{
1
for
⁢
⁢

t

<
T
p
2
0
otherwise
F
ϕ
⁢
⁢
2
=
∑
n
=
0
∞
⁢
⁢
x
⁡
[
t
-
n
⁢
⁢
T
ϕ
⁢
⁢
2
-
ϕ
]
,
where t is a time corresponding to a center of an output pulse, Tp is the width of the output pulse, and Tφ2 is the period of the pulse train, and wherein PK2 and PC2 are respectively given by
P
K2
=
ϕ
2
2
⁢
π
·
K
MAX
⁢
⁢
and
⁢
⁢
P
C2
=
[
K
MAX
-
Frac
⁡
(
P
K2
K
)
]
⁢
C
MAX
.

197 more elements

A programmable skew clock signal generator circuit, comprising:

a reference frequency accumulator clocked by a reference frequency and receiving a constant K0 as an input, the frequency accumulator having a maximum count KMAX and producing an output and an overflow output;
a reference phase accumulator receiving a phase offset constant C0 as an input thereto, the phase accumulator having a maximum count CMAX and producing a phase accumulator output;
a first adder clocked by the reference frequency that adds the accumulator output with a value PK1 to produce a first adder overflow output;
a second adder clocked by the first adder overflow output that adds the reference phase accumulator output with a value PC1 to produce a second adder output;
a delay line clocked by the reference signal Fref and producing a plurality of delayed reference clock signals at a plurality of tap outputs;
and
tap selecting means receiving the reference phase accumulator output and selecting at least one of the tap outputs in response thereto to produce an output Fφ0, and receiving the second adder output and selecting at least one of the tap outputs in response thereto to produce an output Fφ1;
wherein a phase shift φ1 relative to Fφ0 is a function of PK1 and PC1.

5 more elements

Dependencies are inferred from the claim text.

Description4,657 words

Summary311 words

#This invention relates generally to the field of skew correction of clock signals. More particularly, in accordance with certain embodiments consistent with the present invention, this invention relates to a clock de-skewing arrangement that utilizes a delay line architecture.

#Clock skew problems can manifest themselves in several environments, including but not limited to, chip-level, System-on-Chip (SoC), and board/system level. As an example of chip-level skew, consider a microprocessor whose synchronous circuitry (i.e. flip-flops) is spread across a wide area of an integrated circuit chip. Now consider a single clock signal that is to be distributed across the chip in such a way that the rising edge of each clock cycle reaches each flip-flop at the same point in time. Skew in this environment is becoming a more problematic issue as device sizes shrink, clock speeds increase, and chip size increase. This means that the path delay in a signal trace may differ by many cycles of a clock period from one section of the chip to another. With system clock frequencies well into the gigahertz range, clock skews on the order of picoseconds can produce adverse affects on system performance, or even disrupt system functionality.

#A similar problem arises in so-called “System-on-Chip” scenarios. A clock signal should be routed to a baseband section, a microprocessor, and a memory block (or other functional blocks) with minimal skew. Again, the length of an on-chip signal path from the clock generator to the various functional blocks can be long enough to introduce significant delay and thereby affect the maximum operating frequency. Skew can also be a problem on a board level system for the same reasons outlined above. But on a board level system, the problem can be even further exacerbated by even longer signal traces and more severe loading caused by signal paths that are routed on and off chips and other components.

Brief description of the drawings5 figures

#The features of the invention believed to be novel are set forth with particularity in the appended claims. The invention itself however, both as to organization and method of operation, together with objects and advantages thereof, may be best understood by reference to the following detailed description of the invention, which describes certain exemplary embodiments of the invention, taken in conjunction with the accompanying drawings in which:

#FIG. 1 is a schematic diagram of a programmable skew clock circuit consistent with certain embodiments of the present invention;

#FIG. 2 is a graph depicting exemplary programmed output signals from circuit 100 as they relate to a reference clock input signal and to each other, consistent with certain embodiments of the present invention;

Detailed description4,161 words

#While this invention is susceptible of embodiment in many different forms, there is shown in the drawings and will herein be described in detail specific embodiments, with the understanding that the present disclosure is to be considered as an example of the principles of the invention and not intended to limit the invention to the specific embodiments shown and described. In the description below, like reference numerals are used to describe the same, similar or corresponding elements in the several views of the drawings.

#The terms “a” or “an”, as used herein, are defined as one or more than one. The term “plurality”, as used herein, is defined as two or more than two. The term “another”, as used herein, is defined as at least a second or more. The terms “including” and/or “having”, as used herein, are defined as comprising (i.e., open language). The term “coupled”, as used herein, is defined as connected, although not necessarily directly, and not necessarily mechanically.

#This invention, in certain embodiments consistent therewith, provides a flexible, integrated solution whereby a clock de-skew operation is performed within the clock generation function. Due to the inherent nature of the clock generation, the adjustable phase resolution of the output signal(s) can be made very fine as will be demonstrated below.

Facts

Application

10/464,239Filed 18 Jun 2003

Published

US 2004/0257130 A123 Dec 2004

Granted

25 Oct 2005

Term ended

31 Dec 2023

Estimated · how

20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment, including 196 days of adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification5 codes

H03L 7/0812
Provided with an additional controlled phase shifter: and where no voltage or current controlled oscillator is used
G06F 1/06
Generating or distributing clock signals or signals derived directly therefrom: clock generators producing several clock signals
H03L 7/0816
And where no voltage or current controlled oscillator is used: the controlled phase shifter and the frequency- or phase-detection arrangement…
H03L
Automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or

Timeline

18 Jun 2003Application filedUS 10/464,239
18 Jun 2003Assigned to Motorola, Inc., Illinoisassignment of assignor's interest
2 Feb 2004Assigned to Motorola, Inc., Illinoiscorrective assignment due to pto error of misspelled names of cafaro. previously assignment recorded at reel/frame 014202/0086.
23 Dec 2004PublishedUS 2004/0257130 A1
25 Oct 2005GrantedUS 6,959,397 B2
6 Apr 2011Assigned to Motorola Solutions, Inc.change of name
31 Dec 2023Term endedEstimated, includes 196 days of adjustment

Programmable skew clock signal generator selecting one of a plurality of delayed reference clock signals in response to a phase accumulator output

Life of this patent

Programmable skew clock signal generator selecting one of a plurality of delayed reference clock signals in response to a phase accumulator output

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims25

Description4,657 words

Drawings

Description4,657 words

Classification5 codes

Life of this patent