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US 6,959,377 B2Granted
Method and system for managing registers
AssigneeSun Microsystems, Inc.
InventorsSpencer M. Gold, Masooma Bhiawala
Life of this patent
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Abstract
A system and method for memory structures for efficient tracking and recycling of physical register assignments are disclosed. The method and system provide the necessary functionality to allow the number of physical registers assigned to incoming instructions to equal the number of physical registers that are returned to the list of free registers each cycle, thereby maintaining a substantially constant number of physical register pointers in the list of free registers. The system and method reduce the size of the memory structures utilized to track the usage of physical registers and the recycling of these registers.
Claims36
A method for managing physical registers in a microprocessor, said method comprising the steps of:
- a) providing a free physical register list for holding information indicative of a status of the physical registers for managing the physical registers;
- b) fetching a first instruction that causes a first destination register to be mapped to a first physical register;
- c) fetching a second instruction that causes a condition code register and a second destination register to be mapped to a second physical register;
- d) fetching a third instruction that causes the condition code register and the first destination register to be mapped to a third physical register;
- and
- e) writing a pointer to the first physical register into the free physical register list,
- wherein the free physical register lists maintains a substantially constant number of physical register pointers.
4 more elements
A method for managing physical registers in a microprocessor, said method comprising the steps of:
- a) providing a free physical register list for holding information indicative of a status of the physical registers;
- b) fetching a first instruction that causes a first destination register to be mapped to a first physical register;
- c) fetching a second instruction that causes a condition code register to be mapped to a second physical register, said second instruction also including an arithmetic operation producing a result that is mapped to a naught register;
- d) fetching a third instruction that causes the condition code register and the first destination register to be mapped to a third physical register;
- e) writing a pointer to the first physical register into the free physical register list;
- and
- f) moving a pointer to the second physical register into a hold register,
- wherein the pointer to the second register in the hold register is returned to the free physical register list when an instruction does not free a physical register.
5 more elements
A method for managing physical registers in a microprocessor, said method comprising the steps of:
- a) providing a free physical register list for holding information indicative of a status of the physical registers;
- b) fetching a first instruction that causes a first destination register to be mapped to a first physical register;
- c) fetching a second instruction that causes a condition code register to be mapped to a second physical register, said second instruction also including an arithmetic operation producing a result that is mapped to a naught register;
- d) fetching a third instruction that causes the condition code register and the first destination register to be mapped to a third physical register;
- e) writing a pointer to the second physical register into the free physical register list;
- and
- f) moving a pointer to the first physical register into a hold registers,
- wherein the pointer to the first register in the hold register is returned to the free physical register list when an instruction does not free a physical register.
5 more elements
A system for managing physical registers in a microprocessor, said system comprising
- a free physical register list;
- a memory array for storing first, second, and third instructions;
- and
- a instruction fetching unit for
- fetching the first instruction that causes a first destination register to be mapped to a first physical register;
- fetching the second instruction that causes a condition code register and a second destination register to be mapped to a second physical register;
- and
- fetching the third instruction that causes the condition code register and the first destination register to be mapped to a third physical register;
- wherein a pointer to the first physical register is written into the free physical register list, and the free physical register list maintains a substantially constant number of physical register pointers.
6 more elements
A system for managing physical registers in a microprocessor, said system comprising
- a free physical register list;
- a memory array for storing first, second, and third instructions;
- and
- a instruction fetching unit for
- fetching the first instruction that causes a first destination register to be mapped to a first physical register;
- fetching the second instruction that causes a condition code register to be mapped to a second physical register, said second instruction also including an arithmetic operation producing a result that is mapped to a naught register;
- and
- fetching the third instruction that causes the condition code register and the first destination register to be mapped to a third physical register;
- wherein a pointer to the first physical register is written into the free physical register list, and a pointer to the second physical register is moved into a hold register, and wherein the pointer to the second register in the hold register is returned to the free physical register list when an instruction does not free a physical register.
6 more elements
A system for managing physical registers in a microprocessor, said system comprising
- a free physical register list;
- a memory array for storing a first, second, and third instruction;
- and
- a instruction fetching unit for
- fetching the first instruction that causes a first destination register to be mapped to a first physical register;
- fetching the second instruction that causes a condition code register to be mapped to a second physical register, said second instruction also including an arithmetic operation producing a result that is mapped to a naught register;
- and
- fetching the third instruction that causes the condition code register and the first destination register to be mapped to a third physical register;
- wherein a pointer to the second physical register is written into the free physical register list, and a pointer to the first physical register is moved into a hold register, and wherein the pointer to the first register in the hold register is returned to the free physical register list when an instruction does not free a physical register.
6 more elements
Dependencies are inferred from the claim text.