Integrated circuit containing multiple digital signal processors
AssigneeLSI Logic Corporation
InventorsMark Boike, Alan Phan, Keith Dang, Charles H. Stewart
Life of this patent
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Abstract
The present invention is an integrated circuit containing multiple digital signal processors (DSPs). A single host processor interface is also placed on the chip to connect the multiple DSPs to the host. A separate direct memory access (DMA) unit is provided for each DSP to facilitate flow of data to and from a data memory for each DSP. Each DSP also includes an instruction memory.
Claims20
An integrated circuit comprising:
- a host processor interface;
- a common memory bus coupled to said host processor interface;
- a plurality of memory devices, each of said plurality of memory devices coupled to said common memory bus;
- and
- a plurality of digital signal processors, each one of said plurality of digital signal processors associated with and coupled to a corresponding one of said plurality of memory devices.
An integrated circuit comprising:
- a plurality of digital signal processors;
- a host processor interface coupled to a host processor and to said plurality of digital signal processors;
- a plurality of memory devices, each associated with and coupled to one of said plurality of digital signal processors and each coupled to said host processor interface;
- a plurality of direct memory access devices, each associated with one of said plurality of digital signal processors and each coupled to the memory d vic associated with the respective digital signal processor;
- and
- at least two time division multiplexing devices associate with each digital signal processor and coupled to the direct memory access device associated with each digital signal processor, each time division multiplexing device including a signal port for receiving and sending signals.
An integrated circuit comprising:
- at least two ZSP400 digital signal processors;
- a host processor interface coupled to said at least two ZSP400 digital signal processors;
- an instruction memory module and controller for and coupled to each digital signal processor;
- a data memory module and controller for and coupled to each digital signal processor and to said host processor interface;
- a direct memory access device for and coupled to each data memory module;
- and
- at least two time division multiplexing devices for and coupled to each data memory module.
A method of operating at least two digital signal processors on a single integrated circuit comprising:
- coupling said at least two digital signal processors to a host processor using a single host processor interface coupled to a common memory bus coupled to at least two memory devices coupled to respective ones of said at least two digital signal processors.
A method of operating at least two digital signal processors on a single integrated circuit comprising:
- coupling said at least two digital signal processors to a host processor using a single host processor interface;
- providing an instruction memory and a data memory for each digital signal processor;
- and
- coupling each instruction memory and data memory to its respective digital signal processor and to said host processor interface.
The A method operating at least two digital signal processors on a single integrated circuit comprising:
- coupling said at least two digital signal processors to a host processor using a single host processor interface;
- and
- coupling said digital signal processors to multiple framers by:
- (a) coupling one direct memory access device to each digital signal processor,
- (b) coupling at least two time division multiplexing devices to each direct memory access device;
- and
- (c) coupling one framer to each time division multiplexing device.
A method operating at least two ZSP400 digital signal processors on a single integrated circuit comprising:
- coupling said ZSP400 digital signal processors to a host processor using a single host processor interface;
- and
- coupling said ZSP400 digital signal processors to multiple framers by:
- coupling one direct memory access device to each digital signal processor;
- coupling at least two time division multiplexing devices to each direct memory access device;
- and
- coupling one framer to each time division multiplexing device.
Dependencies are inferred from the claim text.