US 6,959,365 B2Granted

Microcomputer including a flash memory and a flash memory rewrite program stored therein

AssigneeRenesas Technology Corp.

InventorsNaoki Ootani, Yoshio Kasai, Toshihiro Abe, Mitsuru Sugita

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Abstract

A microcomputer with a built-in flash memory is obtained in which the flash memory can be properly rewritten with a rewrite program kept placed on the flash memory and without requiring additional complicated control circuitry. On accepting an erase/write command which constitutes a rewrite command, a flash memory module (2) outputs to a flash memory control circuit (3) a ready status signal RYIBY indicative of a busy state during execution of the series of processing. When the ready status signal RYIBY indicates the busy state, the flash memory control circuit (3) outputs a hold signal HOLD at active “H,” in order to inhibit a CPU (1) from accessing the flash memory module (2). When the ready status signal RYIBY has recovered the ready state, the flash memory control circuit (3) outputs the hold signal HOLD at “L” to allow the CPU (1) to access the flash memory module (2).

Claims13

Dependent claims

A microcomputer, comprising:

a CPU configured to execute instructions;
a flash memory portion divided into a plurality of blocks;
and
a flash memory control circuit for controlling a rewrite operation to said flash memory portion, wherein
said CPU is configured to execute a predetermined program stored in at least one of said plurality of blocks, said predetermined program including instructions for rewriting a block other than said at least one of said plurality of blocks in said flash memory portion;
said flash memory portion is configured to execute the rewrite operation in said block other than said at least one of said plurality of blocks based on a rewrite command, and to output a ready status signal indicating whether said rewrite operation is being executed;
said flash memory control circuit is configured to receive said ready status signal, whereby when said ready status signal indicates that said rewrite operation is to be executed, said flash memory control circuit provides a hold signal to said CPU, wherein said hold signal indicates that predetermined signals required for said CPU to access said flash memory portion should be fixed to constant values;
said predetermined signals include an address signal, a data signal, and a control signal of said flash memory control circuit;
said flash memory control circuit is configured to set a pre-hold signal active after a beginning of receipt of said rewrite command and before an end of the receipt of said rewrite command;
and
said flash memory control circuit is configured to output said hold signal indicating said predetermined signals should be fixed to the constant values when said pre-hold signal is active at the end of the receipt of said rewrite command.

8 more elements

A microcomputer, comprising:

a CPU configured to execute instructions;
a flash memory portion divided into a plurality of blocks;
and
a flash memory control circuit for controlling a rewrite operation to said flash memory portion, wherein
said CPU is configured to execute a predetermined program stored in at least one of said plurality of blocks, said predetermined program including instructions for rewriting a block other than said at least one of said plurality of blocks in said flash memory portion;
said flash memory portion is configured to execute the rewrite operation in said block other than said at least one of said plurality of blocks based on a rewrite command, and to output a ready status signal indicating whether said rewrite operation is being executed;
said flash memory control circuit is configured to receive said ready status signal, whereby when said ready status signal indicates that said rewrite operation is to be executed, said flash memory control circuit provides a hold signal to said CPU, wherein said hold signal indicates that predetermined signals required for said CPU to access said flash memory portion should be fixed to constant values;
said predetermined signals include an address signal, a data signal, and a control signal of said flash memory control circuit;
said flash memory portion is configured to set a rewrite command receipt acknowledge signal active at a beginning of receipt of said rewrite command;
and
said flash memory control circuit is configured to output said hold signal indicating said predetermined signals should be fixed to the constant values when said rewrite command receipt acknowledge signal is active at an end of the receipt of said rewrite command by said flash memory portion.

8 more elements

Dependencies are inferred from the claim text.